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Add Mips16 patterns for sign extend byte and sign extend halfword.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192130 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
2013-10-07 20:46:19 +00:00
parent fb92f46459
commit 42be15fcbe
2 changed files with 31 additions and 0 deletions
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30
lib/Target/Mips/Mips16InstrInfo.td
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@@ -343,6 +343,14 @@ class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
!strconcat(asmstr, "\t $rx"), [], itin> ; !strconcat(asmstr, "\t $rx"), [], itin> ;
class FRR_SF16_ins
<bits<5> _funct, bits<3> _subfunc,
string asmstr, InstrItinClass itin>:
FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
!strconcat(asmstr, "\t $rx"),
[], itin> {
let Constraints = "$rx_ = $rx";
}
// //
// RRR-type instruction format // RRR-type instruction format
// //
@@ -951,6 +959,22 @@ def SaveDecSpF16:
def SbRxRyOffMemX16: def SbRxRyOffMemX16:
FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore; FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
//
// Format: SEB rx MIPS16e
// Purpose: Sign-Extend Byte
// Sign-extend least significant byte in register rx.
//
def SebRx16
: FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
//
// Format: SEH rx MIPS16e
// Purpose: Sign-Extend Halfword
// Sign-extend least significant word in register rx.
//
def SehRx16
: FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
// //
// The Sel(T) instructions are pseudos // The Sel(T) instructions are pseudos
// T means that they use T8 implicitly. // T means that they use T8 implicitly.
@@ -1815,6 +1839,12 @@ def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
def: Mips16Pat<(trap), (Break16)>; def: Mips16Pat<(trap), (Break16)>;
def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
(SebRx16 CPU16Regs:$val)>;
def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
(SehRx16 CPU16Regs:$val)>;
def GotPrologue16: def GotPrologue16:
MipsPseudo16< MipsPseudo16<
(outs CPU16Regs:$rh, CPU16Regs:$rl), (outs CPU16Regs:$rh, CPU16Regs:$rl),

1
test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
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@@ -1,5 +1,6 @@
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 -soft-float -mips16-hard-float < %s | FileCheck %s
define signext i8 @A(i8 %e.0, i8 signext %sum) nounwind { define signext i8 @A(i8 %e.0, i8 signext %sum) nounwind {
entry: entry: