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R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used

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DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0.  When M0 is uninitialized,
then we experience undefined behavior.

This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201097 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2014-02-10 16:58:30 +00:00
parent 835f1c01bf
commit 42faffddb9
5 changed files with 45 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/R600/SILowerControlFlow.cpp
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@ -67,7 +67,7 @@ private:
static char ID;
const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
const SIInstrInfo *TII;
bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
@ -408,7 +408,7 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
}
bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
TII = MF.getTarget().getInstrInfo();
TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
TRI = MF.getTarget().getRegisterInfo();
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
@ -426,6 +426,11 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
Next = llvm::next(I);
MachineInstr &MI = *I;
if (TII->isDS(MI.getOpcode())) {
NeedM0 = true;
NeedWQM = true;
}
switch (MI.getOpcode()) {
default: break;
case AMDGPU::SI_IF:
@ -486,14 +491,6 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
IndirectDst(MI);
break;
case AMDGPU::DS_READ_B32:
NeedWQM = true;
// Fall through
case AMDGPU::DS_WRITE_B32:
case AMDGPU::DS_ADD_U32_RTN:
NeedM0 = true;
break;
case AMDGPU::V_INTERP_P1_F32:
case AMDGPU::V_INTERP_P2_F32:
case AMDGPU::V_INTERP_MOV_F32: