6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-01 00:33:09 +00:00
Code Issues Projects Releases Wiki Activity

Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).

Browse Source 
If there is a store after the load node, then there is a chain, which means
that there is another user. Thus, asking hasOneUser would fail. Instead we
ask hasNUsesOfValue on the 'data' value.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131183 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2011-05-11 14:40:50 +00:00
parent 104e99256d
commit 42febc6e99
5 changed files with 29 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -6566,7 +6566,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
}
}
if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
return SDValue();
// If Idx was -1 above, Elt is going to be -1, so just return undef.

12
test/CodeGen/ARM/vstlane.ll
View File

@ -54,7 +54,8 @@ define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
;CHECK: vst1laneQi8:
;CHECK: vst1.8 {d17[1]}, [r0]
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.8 {d17[1]}, [r0]
%tmp1 = load <16 x i8>* %B
%tmp2 = extractelement <16 x i8> %tmp1, i32 9
store i8 %tmp2, i8* %A, align 8
@ -72,7 +73,8 @@ define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
;CHECK: vst1laneQi32:
;CHECK: vst1.32 {d17[1]}, [r0, :32]
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r0, :32]
%tmp1 = load <4 x i32>* %B
%tmp2 = extractelement <4 x i32> %tmp1, i32 3
store i32 %tmp2, i32* %A, align 8
@ -82,7 +84,8 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
;Check for a post-increment updating store.
define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
;CHECK: vst1laneQi32_update:
;CHECK: vst1.32 {d17[1]}, [r1, :32]!
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r1, :32]!
%A = load i32** %ptr
%tmp1 = load <4 x i32>* %B
%tmp2 = extractelement <4 x i32> %tmp1, i32 3
@ -94,7 +97,8 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
;CHECK: vst1laneQf:
;CHECK: vst1.32 {d17[1]}, [r0]
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r0]
%tmp1 = load <4 x float>* %B
%tmp2 = extractelement <4 x float> %tmp1, i32 3
store float %tmp2, float* %A

13
test/CodeGen/X86/2011-05-09-loaduse.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
;CHECK: test
;CHECK-not: pshufd
;CHECK: ret
define float @test(<4 x float>* %A) nounwind {
entry:
%T = load <4 x float>* %A
%R = extractelement <4 x float> %T, i32 3
store <4 x float><float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>* %A
ret float %R
}

8
test/CodeGen/X86/vec_extract-sse4.ll
View File

@ -1,8 +1,8 @@
; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t
; RUN: grep extractps %t | count 1
; RUN: grep pextrd %t | count 1
; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse41 -o %t
; RUN: not grep extractps %t
; RUN: not grep pextrd %t
; RUN: not grep pshufd %t
; RUN: not grep movss %t
; RUN: grep movss %t | count 2
define void @t1(float* %R, <4 x float>* %P1) nounwind {
%X = load <4 x float>* %P1

6
test/CodeGen/X86/vec_extract.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 -o %t
; RUN: grep movss %t | count 3
; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2,-sse41 -o %t
; RUN: grep movss %t | count 4
; RUN: grep movhlps %t | count 1
; RUN: grep pshufd %t | count 1
; RUN: not grep pshufd %t
; RUN: grep unpckhpd %t | count 1
define void @test1(<4 x float>* %F, float* %f) nounwind {