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Tidy up. 80 column.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144538 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -714,7 +714,7 @@ public:
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bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
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bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
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bool isPostIdxReg() const {
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return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
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return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
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}
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bool isMemNoOffset(bool alignOK = false) const {
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if (!isMemory())
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@ -1101,7 +1101,8 @@ public:
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void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 3 && "Invalid number of operands!");
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assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
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assert(isRegShiftedReg() &&
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"addRegShiftedRegOperands() on non RegShiftedReg!");
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Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
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Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
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Inst.addOperand(MCOperand::CreateImm(
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@ -1110,7 +1111,8 @@ public:
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void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
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assert(isRegShiftedImm() &&
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"addRegShiftedImmOperands() on non RegShiftedImm!");
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Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
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Inst.addOperand(MCOperand::CreateImm(
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ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
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@ -1426,8 +1428,9 @@ public:
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void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
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assert(N == 3 && "Invalid number of operands!");
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unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
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Memory.ShiftImm, Memory.ShiftType);
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unsigned Val =
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ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
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Memory.ShiftImm, Memory.ShiftType);
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Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
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Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
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Inst.addOperand(MCOperand::CreateImm(Val));
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