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Replace TargetRegisterInfo::printReg with a PrintReg class that also works without a TRI instance.

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Print virtual registers numbered from 0 instead of the arbitrary
FirstVirtualRegister. The first virtual register is printed as %vreg0.
TRI::NoRegister is printed as %noreg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-01-09 03:05:53 +00:00
parent 994c727b57
commit 4314268128
15 changed files with 81 additions and 110 deletions
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13
lib/CodeGen/MachineBasicBlock.cpp
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@@ -166,17 +166,6 @@ void MachineBasicBlock::dump() const {
print(dbgs());
}
static inline void OutputReg(raw_ostream &os, unsigned RegNo,
const TargetRegisterInfo *TRI = 0) {
if (RegNo != 0 && TargetRegisterInfo::isPhysicalRegister(RegNo)) {
if (TRI)
os << " %" << TRI->get(RegNo).Name;
else
os << " %physreg" << RegNo;
} else
os << " %reg" << RegNo;
}
StringRef MachineBasicBlock::getName() const {
if (const BasicBlock *LBB = getBasicBlock())
return LBB->getName();
@@ -214,7 +203,7 @@ void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
if (Indexes) OS << '\t';
OS << " Live Ins:";
for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I)
OutputReg(OS, *I, TRI);
OS << PrintReg(*I, TRI);
OS << '\n';
}
// Print the preds of this block according to the CFG.