From 434dd4fd94f5f248492c675e4285e7d67342d4c4 Mon Sep 17 00:00:00 2001 From: Bruno Cardoso Lopes Date: Mon, 1 Jun 2009 19:57:37 +0000 Subject: [PATCH] Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72697 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/ExecutionEngine/JIT/JIT.h | 2 +- lib/Target/ARM/ARM.h | 13 +- lib/Target/ARM/ARMCodeEmitter.cpp | 194 ++++++++++++------------ lib/Target/Alpha/AlphaCodeEmitter.cpp | 44 +++--- lib/Target/PowerPC/PPCCodeEmitter.cpp | 33 ++-- lib/Target/PowerPC/PPCTargetMachine.cpp | 6 +- lib/Target/X86/X86.h | 15 +- lib/Target/X86/X86CodeEmitter.cpp | 92 +++++------ lib/Target/X86/X86TargetMachine.cpp | 8 +- 9 files changed, 208 insertions(+), 199 deletions(-) diff --git a/lib/ExecutionEngine/JIT/JIT.h b/lib/ExecutionEngine/JIT/JIT.h index 9924d0bfa9e..3ccb2dd8126 100644 --- a/lib/ExecutionEngine/JIT/JIT.h +++ b/lib/ExecutionEngine/JIT/JIT.h @@ -51,7 +51,7 @@ public: class JIT : public ExecutionEngine { TargetMachine &TM; // The current target we are compiling to TargetJITInfo &TJI; // The JITInfo for the target we are compiling to - JITCodeEmitter *JCE; // JCE object + JITCodeEmitter *JCE; // JCE object JITState *jitstate; diff --git a/lib/Target/ARM/ARM.h b/lib/Target/ARM/ARM.h index c582d684bfe..ac7de911cee 100644 --- a/lib/Target/ARM/ARM.h +++ b/lib/Target/ARM/ARM.h @@ -98,15 +98,10 @@ FunctionPass *createARMCodePrinterPass(raw_ostream &O, FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM, MachineCodeEmitter &MCE); -FunctionPass *createARMCodeEmitterPass( - ARMTargetMachine &TM, MachineCodeEmitter &MCE); -/* -template< class machineCodeEmitter> -FunctionPass *createARMCodeEmitterPass( - ARMTargetMachine &TM, machineCodeEmitter &MCE); -*/ -FunctionPass *createARMJITCodeEmitterPass( - ARMTargetMachine &TM, JITCodeEmitter &JCE); +FunctionPass *createARMCodeEmitterPass( ARMTargetMachine &TM, + MachineCodeEmitter &MCE); +FunctionPass *createARMJITCodeEmitterPass( ARMTargetMachine &TM, + JITCodeEmitter &JCE); FunctionPass *createARMLoadStoreOptimizationPass(); FunctionPass *createARMConstantIslandPass(); diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 70b5d788b48..44fac12019b 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -45,34 +45,31 @@ namespace { class ARMCodeEmitter { public: - /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for /// machine instructions. - unsigned getBinaryCodeForInstr(const MachineInstr &MI); }; - template< class machineCodeEmitter> - class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, - public ARMCodeEmitter - { + template + class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, + public ARMCodeEmitter { ARMJITInfo *JTI; const ARMInstrInfo *II; const TargetData *TD; TargetMachine &TM; - machineCodeEmitter &MCE; + CodeEmitter &MCE; const std::vector *MCPEs; const std::vector *MJTEs; bool IsPIC; public: static char ID; - explicit Emitter(TargetMachine &tm, machineCodeEmitter &mce) + explicit Emitter(TargetMachine &tm, CodeEmitter &mce) : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm), MCE(mce), MCPEs(0), MJTEs(0), IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - Emitter(TargetMachine &tm, machineCodeEmitter &mce, + Emitter(TargetMachine &tm, CodeEmitter &mce, const ARMInstrInfo &ii, const TargetData &td) : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm), MCE(mce), MCPEs(0), MJTEs(0), @@ -170,30 +167,28 @@ namespace { void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, intptr_t JTBase = 0); }; - template - char Emitter::ID = 0; + template + char Emitter::ID = 0; } /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code /// to the specified MCE object. namespace llvm { - -FunctionPass *createARMCodeEmitterPass( - ARMTargetMachine &TM, MachineCodeEmitter &MCE) -{ + +FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM, + MachineCodeEmitter &MCE) { return new Emitter(TM, MCE); } -FunctionPass *createARMJITCodeEmitterPass( - ARMTargetMachine &TM, JITCodeEmitter &JCE) -{ +FunctionPass *createARMJITCodeEmitterPass(ARMTargetMachine &TM, + JITCodeEmitter &JCE) { return new Emitter(TM, JCE); } } // end namespace llvm -template< class machineCodeEmitter> -bool Emitter< machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { assert((MF.getTarget().getRelocationModel() != Reloc::Default || MF.getTarget().getRelocationModel() != Reloc::Static) && "JIT relocation model must be set to static or default!"); @@ -222,8 +217,8 @@ bool Emitter< machineCodeEmitter>::runOnMachineFunction(MachineFunction &MF) { /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. /// -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getShiftOp(unsigned Imm) const { +template +unsigned Emitter::getShiftOp(unsigned Imm) const { switch (ARM_AM::getAM2ShiftOpc(Imm)) { default: assert(0 && "Unknown shift opc!"); case ARM_AM::asr: return 2; @@ -237,9 +232,9 @@ unsigned Emitter< machineCodeEmitter>::getShiftOp(unsigned Imm) const { /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) { +template +unsigned Emitter::getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO) { if (MO.isReg()) return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); else if (MO.isImm()) @@ -267,18 +262,19 @@ unsigned Emitter< machineCodeEmitter>::getMachineOpValue(const MachineInstr &MI, /// emitGlobalAddress - Emit the specified address to the code stream. /// -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, - bool NeedStub, intptr_t ACPV) { - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), - Reloc, GV, ACPV, NeedStub)); +template +void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, + bool NeedStub, intptr_t ACPV) { + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, + GV, ACPV, NeedStub)); } /// emitExternalSymbolAddress - Arrange for the address of an external symbol to /// be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { +template +void Emitter::emitExternalSymbolAddress(const char *ES, + unsigned Reloc) { MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, ES)); } @@ -286,8 +282,9 @@ void Emitter< machineCodeEmitter>::emitExternalSymbolAddress(const char *ES, uns /// emitConstPoolAddress - Arrange for the address of an constant pool /// to be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc) { +template +void Emitter::emitConstPoolAddress(unsigned CPI, + unsigned Reloc) { // Tell JIT emitter we'll resolve the address. MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), Reloc, CPI, 0, true)); @@ -296,22 +293,23 @@ void Emitter< machineCodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned R /// emitJumpTableAddress - Arrange for the address of a jump table to /// be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) { +template +void Emitter::emitJumpTableAddress(unsigned JTIndex, + unsigned Reloc) { MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), Reloc, JTIndex, 0, true)); } /// emitMachineBasicBlock - Emit the specified address basic block. -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB, - unsigned Reloc, intptr_t JTBase) { +template +void Emitter::emitMachineBasicBlock(MachineBasicBlock *BB, + unsigned Reloc, intptr_t JTBase) { MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), Reloc, BB, JTBase)); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitWordLE(unsigned Binary) { +template +void Emitter::emitWordLE(unsigned Binary) { #ifndef NDEBUG DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') << Binary << std::dec << "\n"; @@ -319,8 +317,8 @@ void Emitter< machineCodeEmitter>::emitWordLE(unsigned Binary) { MCE.emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitDWordLE(uint64_t Binary) { +template +void Emitter::emitDWordLE(uint64_t Binary) { #ifndef NDEBUG DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') << (unsigned)Binary << std::dec << "\n"; @@ -330,8 +328,8 @@ void Emitter< machineCodeEmitter>::emitDWordLE(uint64_t Binary) { MCE.emitDWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitInstruction(const MachineInstr &MI) { +template +void Emitter::emitInstruction(const MachineInstr &MI) { DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI; NumEmitted++; // Keep track of the # of mi's emitted @@ -397,8 +395,8 @@ void Emitter< machineCodeEmitter>::emitInstruction(const MachineInstr &MI) { } } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) { +template +void Emitter::emitConstPoolInstruction(const MachineInstr &MI) { unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; @@ -465,8 +463,8 @@ void Emitter< machineCodeEmitter>::emitConstPoolInstruction(const MachineInstr & } } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) { +template +void Emitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { const MachineOperand &MO0 = MI.getOperand(0); const MachineOperand &MO1 = MI.getOperand(1); assert(MO1.isImm() && "Not a valid so_imm value!"); @@ -507,8 +505,8 @@ void Emitter< machineCodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) { +template +void Emitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { // It's basically add r, pc, (LJTI - $+8) const TargetInstrDesc &TID = MI.getDesc(); @@ -536,8 +534,8 @@ void Emitter< machineCodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) { +template +void Emitter::emitPseudoMoveInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; // Part of binary is determined by TableGn. @@ -576,15 +574,15 @@ void Emitter< machineCodeEmitter>::emitPseudoMoveInstruction(const MachineInstr emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::addPCLabel(unsigned LabelID) { +template +void Emitter::addPCLabel(unsigned LabelID) { DOUT << " ** LPC" << LabelID << " @ " << (void*)MCE.getCurrentPCValue() << '\n'; JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) { +template +void Emitter::emitPseudoInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; switch (Opcode) { default: @@ -653,8 +651,9 @@ void Emitter< machineCodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) } } -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getMachineSoRegOpValue(const MachineInstr &MI, +template +unsigned Emitter::getMachineSoRegOpValue( + const MachineInstr &MI, const TargetInstrDesc &TID, const MachineOperand &MO, unsigned OpIdx) { @@ -712,8 +711,8 @@ unsigned Emitter< machineCodeEmitter>::getMachineSoRegOpValue(const MachineInstr return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; } -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) { +template +unsigned Emitter::getMachineSoImmOpValue(unsigned SoImm) { // Encode rotate_imm. unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1) << ARMII::SoRotImmShift; @@ -723,9 +722,9 @@ unsigned Emitter< machineCodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) { return Binary; } -template< class machineCodeEmitter> -unsigned Emitter< machineCodeEmitter>::getAddrModeSBit(const MachineInstr &MI, - const TargetInstrDesc &TID) const { +template +unsigned Emitter::getAddrModeSBit(const MachineInstr &MI, + const TargetInstrDesc &TID) const { for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ const MachineOperand &MO = MI.getOperand(i-1); if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) @@ -734,8 +733,9 @@ unsigned Emitter< machineCodeEmitter>::getAddrModeSBit(const MachineInstr &MI, return 0; } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitDataProcessingInstruction(const MachineInstr &MI, +template +void Emitter::emitDataProcessingInstruction( + const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); @@ -798,8 +798,9 @@ void Emitter< machineCodeEmitter>::emitDataProcessingInstruction(const MachineIn emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitLoadStoreInstruction(const MachineInstr &MI, +template +void Emitter::emitLoadStoreInstruction( + const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); @@ -873,9 +874,9 @@ void Emitter< machineCodeEmitter>::emitLoadStoreInstruction(const MachineInstr & emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI, - unsigned ImplicitRn) { +template +void Emitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, + unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); unsigned Form = TID.TSFlags & ARMII::FormMask; bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; @@ -957,8 +958,9 @@ static unsigned getAddrModeUPBits(unsigned Mode) { return Binary; } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { +template +void Emitter::emitLoadStoreMultipleInstruction( + const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -990,8 +992,8 @@ void Emitter< machineCodeEmitter>::emitLoadStoreMultipleInstruction(const Machin emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) { +template +void Emitter::emitMulFrmInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -1028,8 +1030,8 @@ void Emitter< machineCodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitExtendInstruction(const MachineInstr &MI) { +template +void Emitter::emitExtendInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -1066,8 +1068,8 @@ void Emitter< machineCodeEmitter>::emitExtendInstruction(const MachineInstr &MI) emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) { +template +void Emitter::emitMiscArithInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -1105,8 +1107,8 @@ void Emitter< machineCodeEmitter>::emitMiscArithInstruction(const MachineInstr & emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitBranchInstruction(const MachineInstr &MI) { +template +void Emitter::emitBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); if (TID.Opcode == ARM::TPsoft) @@ -1124,8 +1126,8 @@ void Emitter< machineCodeEmitter>::emitBranchInstruction(const MachineInstr &MI) emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitInlineJumpTable(unsigned JTIndex) { +template +void Emitter::emitInlineJumpTable(unsigned JTIndex) { // Remember the base address of the inline jump table. uintptr_t JTBase = MCE.getCurrentPCValue(); JTI->addJumpTableBaseAddr(JTIndex, JTBase); @@ -1144,8 +1146,8 @@ void Emitter< machineCodeEmitter>::emitInlineJumpTable(unsigned JTIndex) { } } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) { +template +void Emitter::emitMiscBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Handle jump tables. @@ -1225,8 +1227,8 @@ static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { return Binary; } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) { +template +void Emitter::emitVFPArithInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -1265,8 +1267,9 @@ void Emitter< machineCodeEmitter>::emitVFPArithInstruction(const MachineInstr &M emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitVFPConversionInstruction(const MachineInstr &MI) { +template +void Emitter::emitVFPConversionInstruction( + const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); unsigned Form = TID.TSFlags & ARMII::FormMask; @@ -1322,8 +1325,8 @@ void Emitter< machineCodeEmitter>::emitVFPConversionInstruction(const MachineIns emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) { +template +void Emitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1357,8 +1360,9 @@ void Emitter< machineCodeEmitter>::emitVFPLoadStoreInstruction(const MachineInst emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { +template +void Emitter::emitVFPLoadStoreMultipleInstruction( + const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1392,8 +1396,8 @@ void Emitter< machineCodeEmitter>::emitVFPLoadStoreMultipleInstruction(const Mac emitWordLE(Binary); } -template< class machineCodeEmitter> -void Emitter< machineCodeEmitter>::emitMiscInstruction(const MachineInstr &MI) { +template +void Emitter::emitMiscInstruction(const MachineInstr &MI) { // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index ab3682bc9c2..f50f007c207 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -32,7 +32,7 @@ namespace { class AlphaCodeEmitter { MachineCodeEmitter &MCE; public: - AlphaCodeEmitter( MachineCodeEmitter &mce) : MCE(mce) {} + AlphaCodeEmitter(MachineCodeEmitter &mce) : MCE(mce) {} /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for @@ -42,25 +42,25 @@ namespace { /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr - unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO); + unsigned getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO); }; - template + template class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, public AlphaCodeEmitter { const AlphaInstrInfo *II; - TargetMachine &TM; - machineCodeEmitter &MCE; + TargetMachine &TM; + CodeEmitter &MCE; public: static char ID; - explicit Emitter(TargetMachine &tm, machineCodeEmitter &mce) - : MachineFunctionPass(&ID), AlphaCodeEmitter( mce), + explicit Emitter(TargetMachine &tm, CodeEmitter &mce) + : MachineFunctionPass(&ID), AlphaCodeEmitter(mce), II(0), TM(tm), MCE(mce) {} - Emitter(TargetMachine &tm, machineCodeEmitter &mce, - const AlphaInstrInfo& ii) - : MachineFunctionPass(&ID), AlphaCodeEmitter( mce), + Emitter(TargetMachine &tm, CodeEmitter &mce, const AlphaInstrInfo& ii) + : MachineFunctionPass(&ID), AlphaCodeEmitter(mce), II(&ii), TM(tm), MCE(mce) {} bool runOnMachineFunction(MachineFunction &MF); @@ -75,25 +75,25 @@ namespace { void emitBasicBlock(MachineBasicBlock &MBB); }; - template - char Emitter::ID = 0; + template + char Emitter::ID = 0; } -/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code -/// to the specified MCE object. +/// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha +/// code to the specified MCE object. -FunctionPass *llvm::createAlphaCodeEmitterPass( AlphaTargetMachine &TM, +FunctionPass *llvm::createAlphaCodeEmitterPass(AlphaTargetMachine &TM, MachineCodeEmitter &MCE) { return new Emitter(TM, MCE); } -FunctionPass *llvm::createAlphaJITCodeEmitterPass( AlphaTargetMachine &TM, - JITCodeEmitter &JCE) { +FunctionPass *llvm::createAlphaJITCodeEmitterPass(AlphaTargetMachine &TM, + JITCodeEmitter &JCE) { return new Emitter(TM, JCE); } -template -bool Emitter::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo(); do { @@ -105,8 +105,8 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) { return false; } -template -void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { +template +void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { MCE.StartMachineBasicBlock(&MBB); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { @@ -165,7 +165,7 @@ static unsigned getAlphaRegNumber(unsigned Reg) { } unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) { + const MachineOperand &MO) { unsigned rv = 0; // Return value; defaults to 0 for unhandled cases // or things that get fixed up later by the JIT. diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index c3be878a08d..aa3dce19e50 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -23,7 +23,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/Support/Debug.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; @@ -33,8 +33,8 @@ namespace { TargetMachine &TM; MachineCodeEmitter &MCE; public: - PPCCodeEmitter( TargetMachine &tm, MachineCodeEmitter &mce) : - TM( tm), MCE( mce) {} + PPCCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce): + TM(tm), MCE(mce) {} /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for @@ -44,7 +44,8 @@ namespace { /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr - unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO); + unsigned getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO); /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record /// its address in the function into this pointer. @@ -52,12 +53,12 @@ namespace { void *MovePCtoLROffset; }; - template + template class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, public PPCCodeEmitter { TargetMachine &TM; - machineCodeEmitter &MCE; + CodeEmitter &MCE; void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); @@ -66,8 +67,8 @@ namespace { public: static char ID; - Emitter(TargetMachine &tm, machineCodeEmitter &mce) - : MachineFunctionPass(&ID), PPCCodeEmitter( tm, mce), TM(tm), MCE(mce) {} + Emitter(TargetMachine &tm, CodeEmitter &mce) + : MachineFunctionPass(&ID), PPCCodeEmitter(tm, mce), TM(tm), MCE(mce) {} const char *getPassName() const { return "PowerPC Machine Code Emitter"; } @@ -84,24 +85,24 @@ namespace { unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; } }; - template - char Emitter::ID = 0; + template + char Emitter::ID = 0; } /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code /// to the specified MCE object. FunctionPass *llvm::createPPCCodeEmitterPass(PPCTargetMachine &TM, - MachineCodeEmitter &MCE) { + MachineCodeEmitter &MCE) { return new Emitter(TM, MCE); } FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM, - JITCodeEmitter &JCE) { + JITCodeEmitter &JCE) { return new Emitter(TM, JCE); } -template -bool Emitter::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { assert((MF.getTarget().getRelocationModel() != Reloc::Default || MF.getTarget().getRelocationModel() != Reloc::Static) && "JIT relocation model must be set to static or default!"); @@ -117,8 +118,8 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) { return false; } -template -void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { +template +void Emitter::emitBasicBlock(MachineBasicBlock &MBB) { MCE.StartMachineBasicBlock(&MBB); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){ diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index aeb451b6410..ef3f0fc0421 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -220,7 +220,8 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE) { + bool DumpAsm, + MachineCodeEmitter &MCE) { // Machine code emitter pass for PowerPC. PM.add(createPPCCodeEmitterPass(*this, MCE)); if (DumpAsm) { @@ -234,7 +235,8 @@ bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, JITCodeEmitter &JCE) { + bool DumpAsm, + JITCodeEmitter &JCE) { // Machine code emitter pass for PowerPC. PM.add(createPPCJITCodeEmitterPass(*this, JCE)); if (DumpAsm) { diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index fe0dca61b80..fd13b02e136 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -28,7 +28,8 @@ class raw_ostream; /// createX86ISelDag - This pass converts a legalized DAG into a /// X86-specific DAG, ready for instruction scheduling. /// -FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel); +FunctionPass *createX86ISelDag(X86TargetMachine &TM, + CodeGenOpt::Level OptLevel); /// createX86FloatingPointStackifierPass - This function returns a pass which /// converts floating point register references and pseudo instructions into @@ -53,10 +54,10 @@ FunctionPass *createX86CodePrinterPass(raw_ostream &o, /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code /// to the specified MCE object. -FunctionPass *createX86CodeEmitterPass( - X86TargetMachine &TM, MachineCodeEmitter &MCE); -FunctionPass *createX86JITCodeEmitterPass( - X86TargetMachine &TM, JITCodeEmitter &JCE); +FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM, + MachineCodeEmitter &MCE); +FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, + JITCodeEmitter &JCE); /// createX86EmitCodeToMemory - Returns a pass that converts a register /// allocated function into raw machine code in a dynamically @@ -64,8 +65,8 @@ FunctionPass *createX86JITCodeEmitterPass( /// FunctionPass *createEmitX86CodeToMemory(); -/// createX86MaxStackAlignmentCalculatorPass - This function returns a pass which -/// calculates maximal stack alignment required for function +/// createX86MaxStackAlignmentCalculatorPass - This function returns a pass +/// which calculates maximal stack alignment required for function /// FunctionPass *createX86MaxStackAlignmentCalculatorPass(); diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 47d762585d9..e988a5ca9d0 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -36,22 +36,22 @@ using namespace llvm; STATISTIC(NumEmitted, "Number of machine instructions emitted"); namespace { -template< class machineCodeEmitter> +template class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass { const X86InstrInfo *II; const TargetData *TD; X86TargetMachine &TM; - machineCodeEmitter &MCE; + CodeEmitter &MCE; intptr_t PICBaseOffset; bool Is64BitMode; bool IsPIC; public: static char ID; - explicit Emitter(X86TargetMachine &tm, machineCodeEmitter &mce) + explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce) : MachineFunctionPass(&ID), II(0), TD(0), TM(tm), MCE(mce), PICBaseOffset(0), Is64BitMode(false), IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - Emitter(X86TargetMachine &tm, machineCodeEmitter &mce, + Emitter(X86TargetMachine &tm, CodeEmitter &mce, const X86InstrInfo &ii, const TargetData &td, bool is64) : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm), MCE(mce), PICBaseOffset(0), Is64BitMode(is64), @@ -99,8 +99,8 @@ template< class machineCodeEmitter> bool gvNeedsNonLazyPtr(const GlobalValue *GV); }; -template< class machineCodeEmitter> - char Emitter::ID = 0; +template + char Emitter::ID = 0; } /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code @@ -108,21 +108,19 @@ template< class machineCodeEmitter> namespace llvm { -FunctionPass *createX86CodeEmitterPass( - X86TargetMachine &TM, MachineCodeEmitter &MCE) -{ +FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM, + MachineCodeEmitter &MCE) { return new Emitter(TM, MCE); } -FunctionPass *createX86JITCodeEmitterPass( - X86TargetMachine &TM, JITCodeEmitter &JCE) -{ +FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, + JITCodeEmitter &JCE) { return new Emitter(TM, JCE); } } // end namespace llvm -template< class machineCodeEmitter> -bool Emitter::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { MCE.setModuleInfo(&getAnalysis()); @@ -156,8 +154,8 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) { /// necessary to resolve the address of this block later and emits a dummy /// value. /// -template< class machineCodeEmitter> -void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { +template +void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { // Remember where this reference was and where it is to so we can // deal with it later. MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), @@ -168,8 +166,8 @@ void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock * /// emitGlobalAddress - Emit the specified address to the code stream assuming /// this is part of a "take the address of a global" instruction. /// -template< class machineCodeEmitter> -void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, +template +void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, intptr_t Disp /* = 0 */, intptr_t PCAdj /* = 0 */, bool NeedStub /* = false */, @@ -195,8 +193,9 @@ void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Re /// emitExternalSymbolAddress - Arrange for the address of an external symbol to /// be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { +template +void Emitter::emitExternalSymbolAddress(const char *ES, + unsigned Reloc) { intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, ES, RelocCST)); @@ -209,8 +208,8 @@ void Emitter::emitExternalSymbolAddress(const char *ES, unsi /// emitConstPoolAddress - Arrange for the address of an constant pool /// to be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc, +template +void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp /* = 0 */, intptr_t PCAdj /* = 0 */) { intptr_t RelocCST = 0; @@ -230,8 +229,8 @@ void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Re /// emitJumpTableAddress - Arrange for the address of a jump table to /// be emitted to the current location in the function, and allow it to be PC /// relative. -template< class machineCodeEmitter> -void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc, +template +void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc, intptr_t PCAdj /* = 0 */) { intptr_t RelocCST = 0; if (Reloc == X86::reloc_picrel_word) @@ -247,8 +246,8 @@ void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Re MCE.emitWordLE(0); } -template< class machineCodeEmitter> -unsigned Emitter::getX86RegNum(unsigned RegNo) const { +template +unsigned Emitter::getX86RegNum(unsigned RegNo) const { return II->getRegisterInfo().getX86RegNum(RegNo); } @@ -258,24 +257,27 @@ inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, return RM | (RegOpcode << 3) | (Mod << 6); } -template< class machineCodeEmitter> -void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){ +template +void Emitter::emitRegModRMByte(unsigned ModRMReg, + unsigned RegOpcodeFld){ MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg))); } -template< class machineCodeEmitter> -void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) { +template +void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) { MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0)); } -template< class machineCodeEmitter> -void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) { +template +void Emitter::emitSIBByte(unsigned SS, + unsigned Index, + unsigned Base) { // SIB byte is in the same format as the ModRMByte... MCE.emitByte(ModRMByte(SS, Index, Base)); } -template< class machineCodeEmitter> -void Emitter::emitConstant(uint64_t Val, unsigned Size) { +template +void Emitter::emitConstant(uint64_t Val, unsigned Size) { // Output the constant in little endian byte order... for (unsigned i = 0; i != Size; ++i) { MCE.emitByte(Val & 255); @@ -289,16 +291,16 @@ static bool isDisp8(int Value) { return Value == (signed char)Value; } -template< class machineCodeEmitter> -bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) { +template +bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) { // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer // mechanism as 32-bit mode. return (!Is64BitMode || TM.getSubtarget().isTargetDarwin()) && TM.getSubtarget().GVRequiresExtraLoad(GV, TM, false); } -template< class machineCodeEmitter> -void Emitter::emitDisplacementField(const MachineOperand *RelocOp, +template +void Emitter::emitDisplacementField(const MachineOperand *RelocOp, int DispVal, intptr_t PCAdj) { // If this is a simple integer displacement that doesn't require a relocation, // emit it now. @@ -332,8 +334,8 @@ void Emitter::emitDisplacementField(const MachineOperand *Re } } -template< class machineCodeEmitter> -void Emitter::emitMemModRMByte(const MachineInstr &MI, +template +void Emitter::emitMemModRMByte(const MachineInstr &MI, unsigned Op, unsigned RegOpcodeField, intptr_t PCAdj) { const MachineOperand &Op3 = MI.getOperand(Op+3); @@ -450,8 +452,8 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI, } } -template< class machineCodeEmitter> -void Emitter::emitInstruction( +template +void Emitter::emitInstruction( const MachineInstr &MI, const TargetInstrDesc *Desc) { DOUT << MI; @@ -672,7 +674,8 @@ void Emitter::emitInstruction( getX86RegNum(MI.getOperand(CurOp).getReg())); CurOp += 2; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), + X86InstrInfo::sizeOfImm(Desc)); break; case X86II::MRMSrcMem: { @@ -692,7 +695,8 @@ void Emitter::emitInstruction( PCAdj); CurOp += AddrOperands + 1; if (CurOp != NumOps) - emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc)); + emitConstant(MI.getOperand(CurOp++).getImm(), + X86InstrInfo::sizeOfImm(Desc)); break; } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index d4673b0cb05..8264462506a 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -116,7 +116,7 @@ unsigned X86_64TargetMachine::getModuleMatchQuality(const Module &M) { return getJITMatchQuality()/2; } -X86_32TargetMachine::X86_32TargetMachine(const Module &M, const std::string &FS) +X86_32TargetMachine::X86_32TargetMachine(const Module &M, const std::string &FS) : X86TargetMachine(M, FS, false) { } @@ -221,7 +221,8 @@ bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, MachineCodeEmitter &MCE) { + bool DumpAsm, + MachineCodeEmitter &MCE) { // FIXME: Move this to TargetJITInfo! // On Darwin, do not override 64-bit setting made in X86TargetMachine(). if (DefRelocModel == Reloc::Default && @@ -250,7 +251,8 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - bool DumpAsm, JITCodeEmitter &JCE) { + bool DumpAsm, + JITCodeEmitter &JCE) { // FIXME: Move this to TargetJITInfo! // On Darwin, do not override 64-bit setting made in X86TargetMachine(). if (DefRelocModel == Reloc::Default &&