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Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-02-06 17:17:30 +00:00
parent b3a021cdb3
commit 4350eb86a7
4 changed files with 14 additions and 13 deletions
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7
include/llvm/Target/TargetInstrInfo.h
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@@ -427,10 +427,9 @@ public:
return false; return false;
} }
/// IgnoreRegisterClassBarriers - Returns true if pre-register allocation /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
/// live interval splitting pass should ignore barriers of the specified /// instruction that defines the specified register class.
/// register class. virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{
return true; return true;
} }

5
lib/CodeGen/PreAllocSplitting.cpp
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@@ -1128,7 +1128,10 @@ PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs,
// by the current barrier. // by the current barrier.
SmallVector<LiveInterval*, 8> Intervals; SmallVector<LiveInterval*, 8> Intervals;
for (const TargetRegisterClass **RC = RCs; *RC; ++RC) { for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
if (TII->IgnoreRegisterClassBarriers(*RC)) // FIXME: If it's not safe to move any instruction that defines the barrier
// register class, then it means there are some special dependencies which
// codegen is not modelling. Ignore these barriers for now.
if (!TII->isSafeToMoveRegClassDefs(*RC))
continue; continue;
std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC); std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
for (unsigned i = 0, e = VRs.size(); i != e; ++i) { for (unsigned i = 0, e = VRs.size(); i != e; ++i) {

8
lib/Target/X86/X86InstrInfo.cpp
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@@ -2483,11 +2483,11 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
} }
bool X86InstrInfo:: bool X86InstrInfo::
IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const { isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
// FIXME: Ignore bariers of x87 stack registers for now. We can't // FIXME: Return false for x87 stack register classes for now. We can't
// allow any loads of these registers before FpGet_ST0_80. // allow any loads of these registers before FpGet_ST0_80.
return RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass; RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
} }
const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {

7
lib/Target/X86/X86InstrInfo.h
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@@ -406,10 +406,9 @@ public:
virtual virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
/// IgnoreRegisterClassBarriers - Returns true if pre-register allocation /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
/// live interval splitting pass should ignore barriers of the specified /// instruction that defines the specified register class.
/// register class. bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const;
const TargetRegisterClass *getPointerRegClass() const; const TargetRegisterClass *getPointerRegClass() const;