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Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103235 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-05-07 02:04:02 +00:00
parent 07a6d9391c
commit 435d499177
2 changed files with 39 additions and 15 deletions
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44
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -788,14 +788,31 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
}
} else {
assert((RC == ARM::QQPRRegisterClass ||
RC == ARM::QQPR_VFP2RegisterClass ||
RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
llvm_unreachable("Not yet implemented!");
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
.addFrameIndex(FI).addImm(128);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
AddDefaultPred(MIB.addMemOperand(MMO));
} else {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
.addFrameIndex(FI)
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
.addMemOperand(MMO);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_2, 0, TRI);
AddDReg(MIB, SrcReg, ARM::DSUBREG_3, 0, TRI);
}
}
}
@ -847,13 +864,30 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
.addMemOperand(MMO);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
}
} else {
assert((RC == ARM::QQPRRegisterClass ||
RC == ARM::QQPR_VFP2RegisterClass ||
RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
llvm_unreachable("Not yet implemented!");
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
} else {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
.addFrameIndex(FI)
.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
.addMemOperand(MMO);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_2, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::DSUBREG_3, RegState::Define, TRI);
}
}
}

10
lib/Target/ARM/ARMInstrNEON.td
View File

@ -123,11 +123,6 @@ def VLDMQ
: AXDI5<(outs QPR:$dst), (ins addrmode5:$addr, pred:$p),
IndexModeNone, IIC_fpLoadm,
"vldm${addr:submode}${p}\t${addr:base}, ${dst:dregpair}", "", []>;
def VLDMQ_UPD
: AXDI5<(outs QPR:$dst, GPR:$wb), (ins addrmode5:$addr, pred:$p),
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t${addr:base}!, ${dst:dregpair}",
"$addr.base = $wb", []>;
} // mayLoad = 1
let mayStore = 1 in {
@ -138,11 +133,6 @@ def VSTMQ
: AXDI5<(outs), (ins QPR:$src, addrmode5:$addr, pred:$p),
IndexModeNone, IIC_fpStorem,
"vstm${addr:submode}${p}\t${addr:base}, ${src:dregpair}", "", []>;
def VSTMQ_UPD
: AXDI5<(outs GPR:$wb), (ins QPR:$src, addrmode5:$addr, pred:$p),
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t${addr:base}!, ${src:dregpair}",
"$addr.base = $wb", []>;
} // mayStore = 1
let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {