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Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom comments for implicit defs
For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers, while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be emitted as a true PTX register name. Other targets can use this to customize the output of implicit def comments. Fixes PR17519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192444 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -286,6 +286,10 @@ namespace llvm {
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virtual bool
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isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
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/// emitImplicitDef - Targets can override this to customize the output of
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/// IMPLICIT_DEF instructions in verbose mode.
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virtual void emitImplicitDef(const MachineInstr *MI) const;
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//===------------------------------------------------------------------===//
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// Symbol Lowering Routines.
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//===------------------------------------------------------------------===//
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@ -527,11 +527,11 @@ static void emitComments(const MachineInstr &MI, raw_ostream &CommentOS) {
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/// emitImplicitDef - This method emits the specified machine instruction
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/// that is an implicit def.
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static void emitImplicitDef(const MachineInstr *MI, AsmPrinter &AP) {
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void AsmPrinter::emitImplicitDef(const MachineInstr *MI) const {
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unsigned RegNo = MI->getOperand(0).getReg();
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AP.OutStreamer.AddComment(Twine("implicit-def: ") +
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AP.TM.getRegisterInfo()->getName(RegNo));
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AP.OutStreamer.AddBlankLine();
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OutStreamer.AddComment(Twine("implicit-def: ") +
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TM.getRegisterInfo()->getName(RegNo));
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OutStreamer.AddBlankLine();
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}
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static void emitKill(const MachineInstr *MI, AsmPrinter &AP) {
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@ -721,7 +721,7 @@ void AsmPrinter::EmitFunctionBody() {
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}
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break;
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case TargetOpcode::IMPLICIT_DEF:
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if (isVerbose()) emitImplicitDef(II, *this);
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if (isVerbose()) emitImplicitDef(II);
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break;
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case TargetOpcode::KILL:
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if (isVerbose()) emitKill(II, *this);
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@ -551,6 +551,19 @@ void NVPTXAsmPrinter::EmitFunctionBodyEnd() {
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VRegMapping.clear();
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}
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void NVPTXAsmPrinter::emitImplicitDef(const MachineInstr *MI) const {
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unsigned RegNo = MI->getOperand(0).getReg();
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const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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if (TRI->isVirtualRegister(RegNo)) {
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OutStreamer.AddComment(Twine("implicit-def: ") +
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getVirtualRegisterName(RegNo));
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} else {
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OutStreamer.AddComment(Twine("implicit-def: ") +
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TM.getRegisterInfo()->getName(RegNo));
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}
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OutStreamer.AddBlankLine();
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}
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void NVPTXAsmPrinter::emitKernelFunctionDirectives(const Function &F,
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raw_ostream &O) const {
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// If the NVVM IR has some of reqntid* specified, then output
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@ -602,23 +615,30 @@ void NVPTXAsmPrinter::emitKernelFunctionDirectives(const Function &F,
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O << ".minnctapersm " << mincta << "\n";
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}
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void NVPTXAsmPrinter::getVirtualRegisterName(unsigned vr, bool isVec,
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raw_ostream &O) {
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const TargetRegisterClass *RC = MRI->getRegClass(vr);
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std::string
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NVPTXAsmPrinter::getVirtualRegisterName(unsigned Reg) const {
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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DenseMap<unsigned, unsigned> ®map = VRegMapping[RC];
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unsigned mapped_vr = regmap[vr];
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std::string Name;
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raw_string_ostream NameStr(Name);
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if (!isVec) {
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O << getNVPTXRegClassStr(RC) << mapped_vr;
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return;
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}
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report_fatal_error("Bad register!");
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VRegRCMap::const_iterator I = VRegMapping.find(RC);
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assert(I != VRegMapping.end() && "Bad register class");
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const DenseMap<unsigned, unsigned> &RegMap = I->second;
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VRegMap::const_iterator VI = RegMap.find(Reg);
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assert(VI != RegMap.end() && "Bad virtual register");
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unsigned MappedVR = VI->second;
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NameStr << getNVPTXRegClassStr(RC) << MappedVR;
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NameStr.flush();
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return Name;
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}
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void NVPTXAsmPrinter::emitVirtualRegister(unsigned int vr, bool isVec,
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void NVPTXAsmPrinter::emitVirtualRegister(unsigned int vr,
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raw_ostream &O) {
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getVirtualRegisterName(vr, isVec, O);
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O << getVirtualRegisterName(vr);
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}
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void NVPTXAsmPrinter::printVecModifiedImmediate(
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@ -2041,7 +2061,7 @@ void NVPTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
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else
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O << NVPTXInstPrinter::getRegisterName(MO.getReg());
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} else {
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emitVirtualRegister(MO.getReg(), false, O);
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emitVirtualRegister(MO.getReg(), O);
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}
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return;
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@ -188,6 +188,7 @@ private:
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void EmitFunctionEntryLabel();
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void EmitFunctionBodyStart();
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void EmitFunctionBodyEnd();
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void emitImplicitDef(const MachineInstr *MI) const;
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void EmitInstruction(const MachineInstr *);
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void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
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@ -213,7 +214,7 @@ private:
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void emitGlobals(const Module &M);
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void emitHeader(Module &M, raw_ostream &O);
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void emitKernelFunctionDirectives(const Function &F, raw_ostream &O) const;
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void emitVirtualRegister(unsigned int vr, bool isVec, raw_ostream &O);
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void emitVirtualRegister(unsigned int vr, raw_ostream &);
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void emitFunctionExternParamList(const MachineFunction &MF);
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void emitFunctionParamList(const Function *, raw_ostream &O);
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void emitFunctionParamList(const MachineFunction &MF, raw_ostream &O);
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@ -294,7 +295,7 @@ public:
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bool ignoreLoc(const MachineInstr &);
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virtual void getVirtualRegisterName(unsigned, bool, raw_ostream &);
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std::string getVirtualRegisterName(unsigned) const;
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DebugLoc prevDebugLoc;
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void emitLineNumberAsDotLoc(const MachineInstr &);
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9
test/CodeGen/NVPTX/implicit-def.ll
Normal file
9
test/CodeGen/NVPTX/implicit-def.ll
Normal file
@ -0,0 +1,9 @@
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; RUN: llc < %s -O0 -march=nvptx -mcpu=sm_20 -asm-verbose=1 | FileCheck %s
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; CHECK: // implicit-def: %f[[F0:[0-9]+]]
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; CHECK: add.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, %f[[F0]];
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define float @foo(float %a) {
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%ret = fadd float %a, undef
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ret float %ret
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}
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