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Introduce MCCodeGenInfo, which keeps information that can affect codegen

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(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2011-07-19 06:37:02 +00:00
parent 939ece1b5c
commit 439661395f
74 changed files with 641 additions and 314 deletions
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24
lib/Target/Sparc/SparcTargetMachine.cpp
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@@ -24,10 +24,10 @@ extern "C" void LLVMInitializeSparcTarget() {
/// SparcTargetMachine ctor - Create an ILP32 architecture model
///
SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS, bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS),
SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS, is64bit),
DataLayout(Subtarget.getDataLayout()),
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
@@ -51,15 +51,15 @@ bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
}
SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS)
: SparcTargetMachine(T, TT, CPU, FS, false) {
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: SparcTargetMachine(T, TT, CPU, FS, RM, false) {
}
SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS)
: SparcTargetMachine(T, TT, CPU, FS, true) {
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: SparcTargetMachine(T, TT, CPU, FS, RM, true) {
}