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Move even more functionality from MRegisterInfo into TargetInstrInfo.

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Some day I'll get it all moved over...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2008-01-07 01:35:02 +00:00
parent 93f96d00bf
commit 43dbe05279
30 changed files with 1599 additions and 1630 deletions
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79
lib/Target/PowerPC/PPCRegisterInfo.cpp
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@@ -298,85 +298,6 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const {
if (Ops.size() != 1) return NULL;
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI->getOpcode();
unsigned OpNum = Ops[0];
MachineInstr *NewMI = NULL;
if ((Opc == PPC::OR &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
FrameIndex);
}
} else if ((Opc == PPC::OR8 &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRD) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRS) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
}
}
if (NewMI)
NewMI->copyKillDeadInfo(MI);
return NewMI;
}
bool PPCRegisterInfo::canFoldMemoryOperand(MachineInstr *MI,
SmallVectorImpl<unsigned> &Ops) const {
if (Ops.size() != 1) return false;
// Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
// it takes more than one instruction to store it.
unsigned Opc = MI->getOpcode();
if ((Opc == PPC::OR &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
return true;
else if ((Opc == PPC::OR8 &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
return true;
else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
return true;
return false;
}
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//