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This target doesn't support fabs/fneg yet.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-04-02 05:03:24 +00:00
parent 2c8086f4b9
commit 43fdea070c
4 changed files with 15 additions and 0 deletions
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4
lib/Target/Alpha/AlphaISelPattern.cpp
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@ -75,6 +75,10 @@ namespace {
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
// We don't support these yet.
setOperationAction(ISD::FNEG , MVT::f64 , Expand);
setOperationAction(ISD::FABS , MVT::f64 , Expand);
//Doesn't work yet
setOperationAction(ISD::SETCC , MVT::f32, Promote);

3
lib/Target/IA64/IA64ISelPattern.cpp
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@ -80,6 +80,9 @@ namespace {
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
// We don't support these yet.
setOperationAction(ISD::FNEG , MVT::f64 , Expand);
setOperationAction(ISD::FABS , MVT::f64 , Expand);
computeRegisterProperties();

4
lib/Target/PowerPC/PPCISelPattern.cpp
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@ -53,6 +53,10 @@ namespace {
// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
// We don't support these yet.
setOperationAction(ISD::FNEG , MVT::f64 , Expand);
setOperationAction(ISD::FABS , MVT::f64 , Expand);
addLegalFPImmediate(+0.0); // Necessary for FSEL
addLegalFPImmediate(-0.0); //

4
lib/Target/X86/X86ISelPattern.cpp
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@ -63,6 +63,10 @@ namespace {
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
setOperationAction(ISD::SREM , MVT::f64 , Expand);
// We don't support these yet.
setOperationAction(ISD::FNEG , MVT::f64 , Expand);
setOperationAction(ISD::FABS , MVT::f64 , Expand);
// These should be promoted to a larger select which is supported.
/**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);