diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 6e46ab39c89..5fc062463c4 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -136,6 +136,10 @@ public: delete removeFromParent(); } + /// isLabel - Returns true if the MachineInstr represents a label. + /// + bool isLabel() const; + /// isDebugLabel - Returns true if the MachineInstr represents a debug label. /// bool isDebugLabel() const; diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 345864de961..6e9a23955ca 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -225,6 +225,7 @@ public: SDOperand getRegister(unsigned Reg, MVT VT); SDOperand getDbgStopPoint(SDOperand Root, unsigned Line, unsigned Col, const CompileUnitDesc *CU); + SDOperand getLabel(unsigned Opcode, SDOperand Root, unsigned LabelID); SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N) { return getNode(ISD::CopyToReg, MVT::Other, Chain, diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index addf3558060..caa077d0036 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -482,14 +482,11 @@ namespace ISD { // Operand #last: Optional, an incoming flag. INLINEASM, - // LABEL - Represents a label in mid basic block used to track - // locations needed for debug and exception handling tables. This node - // returns a chain. - // Operand #0 : input chain. - // Operand #1 : module unique number use to identify the label. - // Operand #2 : 0 indicates a debug label (e.g. stoppoint), 1 indicates - // a EH label, 2 indicates unknown label type. - LABEL, + // DBG_LABEL, EH_LABEL - Represents a label in mid basic block used to track + // locations needed for debug and exception handling tables. These nodes + // take a chain as input and return a chain. + DBG_LABEL, + EH_LABEL, // DECLARE - Represents a llvm.dbg.declare intrinsic. It's used to track // local variable declarations for debugging information. First operand is @@ -642,8 +639,7 @@ namespace ISD { bool isScalarToVector(const SDNode *N); /// isDebugLabel - Return true if the specified node represents a debug - /// label (i.e. ISD::LABEL or TargetInstrInfo::LABEL node and third operand - /// is 0). + /// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). bool isDebugLabel(const SDNode *N); //===--------------------------------------------------------------------===// @@ -1859,7 +1855,6 @@ protected: InitOperands(&Chain, 1); } public: - unsigned getLine() const { return Line; } unsigned getColumn() const { return Column; } const CompileUnitDesc *getCompileUnit() const { return CU; } @@ -1870,6 +1865,27 @@ public: } }; +class LabelSDNode : public SDNode { + SDUse Chain; + unsigned LabelID; + virtual void ANCHOR(); // Out-of-line virtual method to give class a home. +protected: + friend class SelectionDAG; + LabelSDNode(unsigned NodeTy, SDOperand ch, unsigned id) + : SDNode(NodeTy, getSDVTList(MVT::Other)), LabelID(id) { + Chain = ch; + InitOperands(&Chain, 1); + } +public: + unsigned getLabelID() const { return LabelID; } + + static bool classof(const LabelSDNode *) { return true; } + static bool classof(const SDNode *N) { + return N->getOpcode() == ISD::DBG_LABEL || + N->getOpcode() == ISD::EH_LABEL; + } +}; + class ExternalSymbolSDNode : public SDNode { const char *Symbol; virtual void ANCHOR(); // Out-of-line virtual method to give class a home. diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index a2dc86f4a3a..5c5f0e151c1 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -46,12 +46,14 @@ public: enum { PHI = 0, INLINEASM = 1, - LABEL = 2, - DECLARE = 3, - EXTRACT_SUBREG = 4, - INSERT_SUBREG = 5, - IMPLICIT_DEF = 6, - SUBREG_TO_REG = 7 + DBG_LABEL = 2, + EH_LABEL = 3, + GC_LABEL = 4, + DECLARE = 5, + EXTRACT_SUBREG = 6, + INSERT_SUBREG = 7, + IMPLICIT_DEF = 8, + SUBREG_TO_REG = 9 }; unsigned getNumOpcodes() const { return NumOpcodes; } diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index f629ae75f3a..6825bfb1033 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -114,12 +114,12 @@ void BranchFolder::RemoveDeadBlock(MachineBasicBlock *MBB) { while (!MBB->succ_empty()) MBB->removeSuccessor(MBB->succ_end()-1); - // If there is DWARF info to active, check to see if there are any LABEL + // If there is DWARF info to active, check to see if there are any DBG_LABEL // records in the basic block. If so, unregister them from MachineModuleInfo. if (MMI && !MBB->empty()) { for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) { - if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) { + if ((unsigned)I->getOpcode() == TargetInstrInfo::DBG_LABEL) { // The label ID # is always operand #0, an immediate. MMI->InvalidateLabel(I->getOperand(0).getImm()); } diff --git a/lib/CodeGen/Collector.cpp b/lib/CodeGen/Collector.cpp index 6c5263d73e3..bbb3b938ad9 100644 --- a/lib/CodeGen/Collector.cpp +++ b/lib/CodeGen/Collector.cpp @@ -337,7 +337,7 @@ void MachineCodeAnalysis::getAnalysisUsage(AnalysisUsage &AU) const { unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { unsigned Label = MMI->NextLabelID(); - BuildMI(MBB, MI, TII->get(TargetInstrInfo::LABEL)).addImm(Label).addImm(2); + BuildMI(MBB, MI, TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label); return Label; } diff --git a/lib/CodeGen/DwarfWriter.cpp b/lib/CodeGen/DwarfWriter.cpp index f0687447eba..a33773904f5 100644 --- a/lib/CodeGen/DwarfWriter.cpp +++ b/lib/CodeGen/DwarfWriter.cpp @@ -3260,7 +3260,7 @@ private: I != E; ++I) { for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end(); MI != E; ++MI) { - if (MI->getOpcode() != TargetInstrInfo::LABEL) { + if (!MI->isLabel()) { SawPotentiallyThrowing |= MI->getDesc().isCall(); continue; } diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 18810f21085..75b2c9865ec 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -523,10 +523,18 @@ unsigned MachineInstr::getNumExplicitOperands() const { } +/// isLabel - Returns true if the MachineInstr represents a label. +/// +bool MachineInstr::isLabel() const { + return getOpcode() == TargetInstrInfo::DBG_LABEL || + getOpcode() == TargetInstrInfo::EH_LABEL || + getOpcode() == TargetInstrInfo::GC_LABEL; +} + /// isDebugLabel - Returns true if the MachineInstr represents a debug label. /// bool MachineInstr::isDebugLabel() const { - return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0; + return getOpcode() == TargetInstrInfo::DBG_LABEL; } /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 3665ee0128b..4548894d578 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1084,28 +1084,26 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case TargetLowering::Expand: { MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); - bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); + bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); const DbgStopPointSDNode *DSP = cast(Node); if (MMI && (useDEBUG_LOC || useLABEL)) { const CompileUnitDesc *CompileUnit = DSP->getCompileUnit(); unsigned SrcFile = MMI->RecordSource(CompileUnit); - SmallVector Ops; - Ops.push_back(Tmp1); // chain unsigned Line = DSP->getLine(); unsigned Col = DSP->getColumn(); if (useDEBUG_LOC) { + SmallVector Ops; + Ops.push_back(Tmp1); // chain Ops.push_back(DAG.getConstant(Line, MVT::i32)); // line # Ops.push_back(DAG.getConstant(Col, MVT::i32)); // col # Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); } else { unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); - Ops.push_back(DAG.getConstant(ID, MVT::i32)); - Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label - Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size()); + Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); } } else { Result = Tmp1; // chain @@ -1163,15 +1161,14 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; - case ISD::LABEL: - assert(Node->getNumOperands() == 3 && "Invalid LABEL node!"); - switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { + case ISD::DBG_LABEL: + case ISD::EH_LABEL: + assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); + switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { default: assert(0 && "This action is not supported yet!"); case TargetLowering::Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. - Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand. - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); + Result = DAG.UpdateNodeOperands(Result, Tmp1); break; case TargetLowering::Expand: Result = LegalizeOp(Node->getOperand(0)); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 7194ed0ab60..de2c1bc90aa 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -879,10 +879,17 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone, assert(0 && "EntryToken should have been excluded from the schedule!"); break; case ISD::TokenFactor: // fall thru - case ISD::LABEL: case ISD::DECLARE: case ISD::SRCVALUE: break; + case ISD::DBG_LABEL: + BB->push_back(BuildMI(TII->get(TargetInstrInfo::DBG_LABEL)) + .addImm(cast(Node)->getLabelID())); + break; + case ISD::EH_LABEL: + BB->push_back(BuildMI(TII->get(TargetInstrInfo::EH_LABEL)) + .addImm(cast(Node)->getLabelID())); + break; case ISD::CopyToReg: { unsigned SrcReg; SDOperand SrcVal = Node->getOperand(2); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index c364e1f737d..17a5fa7d846 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -192,19 +192,15 @@ bool ISD::isScalarToVector(const SDNode *N) { /// isDebugLabel - Return true if the specified node represents a debug -/// label (i.e. ISD::LABEL or TargetInstrInfo::LABEL node and third operand -/// is 0). +/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node). bool ISD::isDebugLabel(const SDNode *N) { SDOperand Zero; - if (N->getOpcode() == ISD::LABEL) - Zero = N->getOperand(2); - else if (N->isTargetOpcode() && - N->getTargetOpcode() == TargetInstrInfo::LABEL) - // Chain moved to last operand. - Zero = N->getOperand(1); - else - return false; - return isa(Zero) && cast(Zero)->isNullValue(); + if (N->getOpcode() == ISD::DBG_LABEL) + return true; + if (N->isTargetOpcode() && + N->getTargetOpcode() == TargetInstrInfo::DBG_LABEL) + return true; + return false; } /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) @@ -389,6 +385,10 @@ static void AddNodeIDNode(FoldingSetNodeID &ID, SDNode *N) { ID.AddPointer(DSP->getCompileUnit()); break; } + case ISD::DBG_LABEL: + case ISD::EH_LABEL: + ID.AddInteger(cast(N)->getLabelID()); + break; case ISD::SRCVALUE: ID.AddPointer(cast(N)->getValue()); break; @@ -1018,6 +1018,22 @@ SDOperand SelectionDAG::getDbgStopPoint(SDOperand Root, return SDOperand(N, 0); } +SDOperand SelectionDAG::getLabel(unsigned Opcode, + SDOperand Root, + unsigned LabelID) { + FoldingSetNodeID ID; + SDOperand Ops[] = { Root }; + AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); + ID.AddInteger(LabelID); + void *IP = 0; + if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) + return SDOperand(E, 0); + SDNode *N = new LabelSDNode(Opcode, Root, LabelID); + CSEMap.InsertNode(N, IP); + AllNodes.push_back(N); + return SDOperand(N, 0); +} + SDOperand SelectionDAG::getSrcValue(const Value *V) { assert((!V || isa(V->getType())) && "SrcValue is not a pointer?"); @@ -4202,6 +4218,7 @@ void SrcValueSDNode::ANCHOR() {} void MemOperandSDNode::ANCHOR() {} void RegisterSDNode::ANCHOR() {} void DbgStopPointSDNode::ANCHOR() {} +void LabelSDNode::ANCHOR() {} void ExternalSymbolSDNode::ANCHOR() {} void CondCodeSDNode::ANCHOR() {} void ARG_FLAGSSDNode::ANCHOR() {} @@ -4521,7 +4538,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::UNDEF: return "undef"; case ISD::MERGE_VALUES: return "merge_values"; case ISD::INLINEASM: return "inlineasm"; - case ISD::LABEL: return "label"; + case ISD::DBG_LABEL: return "dbg_label"; + case ISD::EH_LABEL: return "eh_label"; case ISD::DECLARE: return "declare"; case ISD::HANDLENODE: return "handlenode"; case ISD::FORMAL_ARGUMENTS: return "formal_arguments"; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index dc4dcc92a21..8751c9a0860 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3179,9 +3179,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DbgRegionStartInst &RSI = cast(I); if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) { unsigned LabelID = MMI->RecordRegionStart(RSI.getContext()); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), - DAG.getConstant(LabelID, MVT::i32), - DAG.getConstant(0, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); } return 0; @@ -3191,9 +3189,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DbgRegionEndInst &REI = cast(I); if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) { unsigned LabelID = MMI->RecordRegionEnd(REI.getContext()); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), - DAG.getConstant(LabelID, MVT::i32), - DAG.getConstant(0, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID)); } return 0; @@ -3576,9 +3572,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, // Both PendingLoads and PendingExports must be flushed here; // this call might not return. (void)getRoot(); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getControlRoot(), - DAG.getConstant(BeginLabel, MVT::i32), - DAG.getConstant(1, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel)); } std::pair Result = @@ -3595,9 +3589,7 @@ void SelectionDAGLowering::LowerCallTo(CallSite CS, SDOperand Callee, // Insert a label at the end of the invoke call to mark the try range. This // can be used to detect deletion of the invoke via the MachineModuleInfo. EndLabel = MMI->NextLabelID(); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(), - DAG.getConstant(EndLabel, MVT::i32), - DAG.getConstant(1, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel)); // Inform MachineModuleInfo of range. MMI->addInvoke(LandingPad, BeginLabel, EndLabel); @@ -5112,9 +5104,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, // Add a label to mark the beginning of the landing pad. Deletion of the // landing pad can thus be detected via the MachineModuleInfo. unsigned LabelID = MMI->addLandingPad(BB); - DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(), - DAG.getConstant(LabelID, MVT::i32), - DAG.getConstant(1, MVT::i32))); + DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID)); // Mark exception register as live in. unsigned Reg = TLI.getExceptionAddressRegister(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index 5c51cf78101..c0311911d33 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -144,6 +144,8 @@ std::string DOTGraphTraits::getNodeLabel(const SDNode *Node, Op += ":" + utostr(D->getLine()); if (D->getColumn() != 0) Op += ":" + utostr(D->getColumn()); + } else if (const LabelSDNode *L = dyn_cast(Node)) { + Op += ": LabelID=" + utostr(L->getLabelID()); } else if (const ExternalSymbolSDNode *ES = dyn_cast(Node)) { Op += "'" + std::string(ES->getSymbol()) + "'"; diff --git a/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp b/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp index 7f015369d56..842eb25d579 100644 --- a/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp +++ b/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp @@ -325,7 +325,7 @@ unsigned char* JITDwarfEmitter::EmitExceptionTable(MachineFunction* MF, I != E; ++I) { for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end(); MI != E; ++MI) { - if (MI->getOpcode() != TargetInstrInfo::LABEL) { + if (!MI->isLabel()) { MayThrow |= MI->getDesc().isCall(); continue; } @@ -940,7 +940,7 @@ JITDwarfEmitter::GetExceptionTableSizeInBytes(MachineFunction* MF) const { I != E; ++I) { for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end(); MI != E; ++MI) { - if (MI->getOpcode() != TargetInstrInfo::LABEL) { + if (!MI->isLabel()) { MayThrow |= MI->getDesc().isCall(); continue; } diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 94ca6b09fde..f9f10bafe3e 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -891,7 +891,7 @@ unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { // If this machine instr is an inline asm, measure it. if (MI->getOpcode() == ARM::INLINEASM) return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName()); - if (MI->getOpcode() == ARM::LABEL) + if (MI->isLabel()) return 0; if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) return 0; diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 3cf306a1276..83c3a483bc2 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -106,7 +106,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) // We don't have line number support yet. setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); // Not implemented yet. setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index d75e09ee29d..56148968892 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -444,7 +444,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const if (hasDebugInfo) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(FrameLabelId).addImm(0); + BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId); } // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp) @@ -504,7 +504,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const // Mark effective beginning of when frame pointer is ready. unsigned ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(ReadyLabelId).addImm(0); + BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId); MachineLocation FPDst(SPU::R1); MachineLocation FPSrc(MachineLocation::VirtualFP); @@ -518,7 +518,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const MachineBasicBlock::iterator MBBI = prior(MBB.end()); // Insert terminator label unsigned BranchLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0); + BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId); } } } diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 69f0cb1bc7d..fa046726989 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -89,7 +89,8 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) // We don't have line number support yet. setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); // IA64 has ctlz in the form of the 'fnorm' instruction. The Legalizer // expansion for ctlz/cttz in terms of ctpop is much larger, but lower diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index a2fef465fa0..18cedcf7579 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -97,7 +97,8 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) // We don't have line number support yet. setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); // Use the default for now setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index dc44e090e61..78936b8835a 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -135,7 +135,8 @@ PIC16TargetLowering(PIC16TargetMachine &TM): TargetLowering(TM) // We don't have line number support yet. setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); // Use the default for now. setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index 51672be0491..2dfdda3cde6 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -105,7 +105,8 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { default: MCE.emitWordBE(getBinaryCodeForInstr(*I)); break; - case TargetInstrInfo::LABEL: + case TargetInstrInfo::DBG_LABEL: + case TargetInstrInfo::EH_LABEL: MCE.emitLabel(MI.getOperand(0).getImm()); break; case TargetInstrInfo::IMPLICIT_DEF: diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index d7adea3c778..378fa4bf4da 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -754,9 +754,10 @@ unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { const char *AsmStr = MI->getOperand(0).getSymbolName(); return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr); } - case PPC::LABEL: { + case PPC::DBG_LABEL: + case PPC::EH_LABEL: + case PPC::GC_LABEL: return 0; - } default: return 4; // PowerPC instructions are all 4 bytes } diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index d8ea207ecab..7adf87567d7 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -1068,7 +1068,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0); + BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId); } // Adjust stack pointer: r1 += NegFrameSize. @@ -1177,7 +1177,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { // Mark effective beginning of when frame pointer is ready. unsigned ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0); + BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId); MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) : (IsPPC64 ? PPC::X1 : PPC::R1)); diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 6b0593b869e..cd645bfaeae 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -597,7 +597,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) // We don't have line number support yet. setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); // RET must be custom lowered, to meet ABI requirements setOperationAction(ISD::RET , MVT::Other, Custom); @@ -616,7 +617,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) // No debug info support yet. setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); setOperationAction(ISD::DECLARE, MVT::Other, Expand); setStackPointerRegisterToSaveRestore(SP::O6); diff --git a/lib/Target/Target.td b/lib/Target/Target.td index a268e164107..3f897a5e220 100644 --- a/lib/Target/Target.td +++ b/lib/Target/Target.td @@ -342,9 +342,23 @@ def INLINEASM : Instruction { let AsmString = ""; let Namespace = "TargetInstrInfo"; } -def LABEL : Instruction { +def DBG_LABEL : Instruction { let OutOperandList = (ops); - let InOperandList = (ops i32imm:$id, i32imm:$flavor); + let InOperandList = (ops i32imm:$id); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} +def EH_LABEL : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops i32imm:$id); + let AsmString = ""; + let Namespace = "TargetInstrInfo"; + let hasCtrlDep = 1; +} +def GC_LABEL : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops i32imm:$id); let AsmString = ""; let Namespace = "TargetInstrInfo"; let hasCtrlDep = 1; diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp index 94cedef21a9..aaf7d7faf99 100644 --- a/lib/Target/X86/X86ATTAsmPrinter.cpp +++ b/lib/Target/X86/X86ATTAsmPrinter.cpp @@ -272,7 +272,7 @@ bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) { for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end(); II != IE; ++II) { // Print the assembly for the instruction. - if (II->getOpcode() != X86::LABEL) + if (!II->isLabel()) hasAnyRealCode = true; printMachineInstruction(II); } diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 82604a8b59f..1b2d5ffc3e6 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -490,7 +490,8 @@ void Emitter::emitInstruction(const MachineInstr &MI, case TargetInstrInfo::INLINEASM: assert(0 && "JIT does not support inline asm!\n"); break; - case TargetInstrInfo::LABEL: + case TargetInstrInfo::DBG_LABEL: + case TargetInstrInfo::EH_LABEL: MCE.emitLabel(MI.getOperand(0).getImm()); break; case TargetInstrInfo::IMPLICIT_DEF: diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index beb0b6f9070..6923e84b976 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -303,8 +303,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // FIXME - use subtarget debug flags if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() && - !Subtarget->isTargetCygMing()) - setOperationAction(ISD::LABEL, MVT::Other, Expand); + !Subtarget->isTargetCygMing()) { + setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); + } setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index bfc8abbfa1b..218487e94bf 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2681,7 +2681,8 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, FinalSize += AI->getInlineAsmLength(AsmStr); break; } - case TargetInstrInfo::LABEL: + case TargetInstrInfo::DBG_LABEL: + case TargetInstrInfo::EH_LABEL: break; case TargetInstrInfo::IMPLICIT_DEF: case TargetInstrInfo::DECLARE: diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index b48cee3ac33..1f04380f325 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -691,7 +691,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0); + BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); } // Update EBP with the new base value... @@ -710,7 +710,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { if (needsFrameMoves) { // Mark effective beginning of when frame pointer is ready. ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0); + BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); } // Skip the callee-saved push instructions. diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 8fbb2cfbb61..18b07595611 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -363,7 +363,7 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { const AsmWriterInst *Inst = getAsmWriterInstByID(i); - if (Inst == 0) continue; // PHI, INLINEASM, LABEL, etc. + if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc. std::string Command; if (Inst->Operands.empty()) @@ -641,7 +641,7 @@ void AsmWriterEmitter::run(std::ostream &O) { << " O << \"\\t\";\n" << " printInlineAsm(MI);\n" << " return true;\n" - << " } else if (MI->getOpcode() == TargetInstrInfo::LABEL) {\n" + << " } else if (MI->isLabel()) {\n" << " printLabel(MI);\n" << " return true;\n" << " } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {\n" diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index a21a31c2bfc..557a8f4df9a 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -26,7 +26,9 @@ void CodeEmitterGen::reverseBits(std::vector &Insts) { Record *R = *I; if (R->getName() == "PHI" || R->getName() == "INLINEASM" || - R->getName() == "LABEL" || + R->getName() == "DBG_LABEL" || + R->getName() == "EH_LABEL" || + R->getName() == "GC_LABEL" || R->getName() == "DECLARE" || R->getName() == "EXTRACT_SUBREG" || R->getName() == "INSERT_SUBREG" || @@ -102,7 +104,9 @@ void CodeEmitterGen::run(std::ostream &o) { if (R->getName() == "PHI" || R->getName() == "INLINEASM" || - R->getName() == "LABEL" || + R->getName() == "DBG_LABEL" || + R->getName() == "EH_LABEL" || + R->getName() == "GC_LABEL" || R->getName() == "DECLARE" || R->getName() == "EXTRACT_SUBREG" || R->getName() == "INSERT_SUBREG" || @@ -137,7 +141,9 @@ void CodeEmitterGen::run(std::ostream &o) { if (InstName == "PHI" || InstName == "INLINEASM" || - InstName == "LABEL"|| + InstName == "DBG_LABEL"|| + InstName == "EH_LABEL"|| + InstName == "GC_LABEL"|| InstName == "DECLARE"|| InstName == "EXTRACT_SUBREG" || InstName == "INSERT_SUBREG" || diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index 2aae8773fad..a09068e15ba 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -286,9 +286,17 @@ getInstructionsByEnumValue(std::vector if (I == Instructions.end()) throw "Could not find 'INLINEASM' instruction!"; const CodeGenInstruction *INLINEASM = &I->second; - I = getInstructions().find("LABEL"); - if (I == Instructions.end()) throw "Could not find 'LABEL' instruction!"; - const CodeGenInstruction *LABEL = &I->second; + I = getInstructions().find("DBG_LABEL"); + if (I == Instructions.end()) throw "Could not find 'DBG_LABEL' instruction!"; + const CodeGenInstruction *DBG_LABEL = &I->second; + + I = getInstructions().find("EH_LABEL"); + if (I == Instructions.end()) throw "Could not find 'EH_LABEL' instruction!"; + const CodeGenInstruction *EH_LABEL = &I->second; + + I = getInstructions().find("GC_LABEL"); + if (I == Instructions.end()) throw "Could not find 'GC_LABEL' instruction!"; + const CodeGenInstruction *GC_LABEL = &I->second; I = getInstructions().find("DECLARE"); if (I == Instructions.end()) throw "Could not find 'DECLARE' instruction!"; @@ -317,7 +325,9 @@ getInstructionsByEnumValue(std::vector // Print out the rest of the instructions now. NumberedInstructions.push_back(PHI); NumberedInstructions.push_back(INLINEASM); - NumberedInstructions.push_back(LABEL); + NumberedInstructions.push_back(DBG_LABEL); + NumberedInstructions.push_back(EH_LABEL); + NumberedInstructions.push_back(GC_LABEL); NumberedInstructions.push_back(DECLARE); NumberedInstructions.push_back(EXTRACT_SUBREG); NumberedInstructions.push_back(INSERT_SUBREG); @@ -326,7 +336,9 @@ getInstructionsByEnumValue(std::vector for (inst_iterator II = inst_begin(), E = inst_end(); II != E; ++II) if (&II->second != PHI && &II->second != INLINEASM && - &II->second != LABEL && + &II->second != DBG_LABEL && + &II->second != EH_LABEL && + &II->second != GC_LABEL && &II->second != DECLARE && &II->second != EXTRACT_SUBREG && &II->second != INSERT_SUBREG && diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index 5075d483b2c..b3a75de5e59 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -1864,20 +1864,6 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) { << " N.getValueType());\n" << "}\n\n"; - OS << "SDNode *Select_LABEL(const SDOperand &N) {\n" - << " SDOperand Chain = N.getOperand(0);\n" - << " SDOperand N1 = N.getOperand(1);\n" - << " SDOperand N2 = N.getOperand(2);\n" - << " unsigned C1 = cast(N1)->getValue();\n" - << " unsigned C2 = cast(N2)->getValue();\n" - << " SDOperand Tmp1 = CurDAG->getTargetConstant(C1, MVT::i32);\n" - << " SDOperand Tmp2 = CurDAG->getTargetConstant(C2, MVT::i32);\n" - << " AddToISelQueue(Chain);\n" - << " SDOperand Ops[] = { Tmp1, Tmp2, Chain };\n" - << " return CurDAG->getTargetNode(TargetInstrInfo::LABEL,\n" - << " MVT::Other, Ops, 3);\n" - << "}\n\n"; - OS << "SDNode *Select_DECLARE(const SDOperand &N) {\n" << " SDOperand Chain = N.getOperand(0);\n" << " SDOperand N1 = N.getOperand(1);\n" @@ -1956,12 +1942,13 @@ void DAGISelEmitter::EmitInstructionSelector(std::ostream &OS) { << " case ISD::TokenFactor:\n" << " case ISD::CopyFromReg:\n" << " case ISD::CopyToReg: {\n" + << " case ISD::DBG_LABEL:\n" + << " case ISD::EH_LABEL:\n" << " for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)\n" << " AddToISelQueue(N.getOperand(i));\n" << " return NULL;\n" << " }\n" << " case ISD::INLINEASM: return Select_INLINEASM(N);\n" - << " case ISD::LABEL: return Select_LABEL(N);\n" << " case ISD::DECLARE: return Select_DECLARE(N);\n" << " case ISD::EXTRACT_SUBREG: return Select_EXTRACT_SUBREG(N);\n" << " case ISD::INSERT_SUBREG: return Select_INSERT_SUBREG(N);\n" diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index fb8dd371efd..c29f5c48bfa 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -279,7 +279,9 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, // This isn't an error if this is a builtin instruction. if (R->getName() != "PHI" && R->getName() != "INLINEASM" && - R->getName() != "LABEL" && + R->getName() != "DBG_LABEL" && + R->getName() != "EH_LABEL" && + R->getName() != "GC_LABEL" && R->getName() != "DECLARE" && R->getName() != "EXTRACT_SUBREG" && R->getName() != "INSERT_SUBREG" &&