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[PowerPC] Support mtspr/mfspr in the asm parser

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This adds support for the generic forms of mtspr/mfspr
for the asm parser.  The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand 2013-07-03 12:32:41 +00:00
parent fa487e83a8
commit 44175d9715
4 changed files with 28 additions and 15 deletions
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2
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -304,7 +304,7 @@ def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
PPC970_DGroup_First, PPC970_Unit_FXU;
}
let Pattern = [(set i64:$rT, readcyclecounter)] in
let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in
def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
"mfspr $rT, 268", SprMFTB>,
PPC970_DGroup_First, PPC970_Unit_FXU;

29
lib/Target/PowerPC/PPCInstrInfo.td
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@ -1830,6 +1830,12 @@ def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
// XFX-Form instructions. Instructions that deal with SPRs.
//
def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
"mfspr $RT, $SPR", SprMFSPR>;
def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
"mtspr $SPR, $RT", SprMTSPR>;
let Uses = [CTR] in {
def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
"mfctr $rT", SprMFSPR>,
@ -1858,17 +1864,17 @@ def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
PPC970_DGroup_First, PPC970_Unit_FXU;
}
// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
// a GPR on the PPC970. As such, copies in and out have the same performance
// characteristics as an OR instruction.
def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
"mtspr 256, $rS", IntGeneral>,
PPC970_DGroup_Single, PPC970_Unit_FXU;
def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
"mfspr $rT, 256", IntGeneral>,
PPC970_DGroup_First, PPC970_Unit_FXU;
let isCodeGenOnly = 1 in {
// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
// like a GPR on the PPC970. As such, copies in and out have the same
// performance characteristics as an OR instruction.
def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
"mtspr 256, $rS", IntGeneral>,
PPC970_DGroup_Single, PPC970_Unit_FXU;
def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
"mfspr $rT, 256", IntGeneral>,
PPC970_DGroup_First, PPC970_Unit_FXU;
def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
(outs VRSAVERC:$reg), (ins gprc:$rS),
"mtspr 256, $rS", IntGeneral>,
@ -2321,6 +2327,9 @@ def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
def : InstAlias<"xnop", (XORI R0, R0, 0)>;
def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;

6
test/MC/PowerPC/ppc64-encoding-ext.s
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@ -1953,8 +1953,10 @@
# Move to/from special purpose register mnemonics
# FIXME: mtxer 2
# FIXME: mfxer 2
# CHECK: mtspr 1, 2 # encoding: [0x7c,0x41,0x03,0xa6]
mtxer 2
# CHECK: mfspr 2, 1 # encoding: [0x7c,0x41,0x02,0xa6]
mfxer 2
# CHECK: mtlr 2 # encoding: [0x7c,0x48,0x03,0xa6]
mtlr 2
# CHECK: mflr 2 # encoding: [0x7c,0x48,0x02,0xa6]

6
test/MC/PowerPC/ppc64-encoding.s
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@ -504,8 +504,10 @@
# Move to/from system register instructions
# FIXME: mtspr 256, 2
# FIXME: mfspr 2, 256
# CHECK: mtspr 600, 2 # encoding: [0x7c,0x58,0x93,0xa6]
mtspr 600, 2
# CHECK: mfspr 2, 600 # encoding: [0x7c,0x58,0x92,0xa6]
mfspr 2, 600
# CHECK: mtcrf 16, 2 # encoding: [0x7c,0x41,0x01,0x20]
mtcrf 16, 2
# CHECK: mfcr 2 # encoding: [0x7c,0x40,0x00,0x26]