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https://github.com/c64scene-ar/llvm-6502.git
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Add CALL lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70727 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
01e0e8d119
commit
4428885c5a
@ -70,8 +70,9 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::SRA: return LowerShifts(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::SRA: return LowerShifts(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::CALL: return LowerCALL(Op, DAG);
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default:
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assert(0 && "unimplemented operand");
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return SDValue();
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@ -96,6 +97,18 @@ SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
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}
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}
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SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
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unsigned CallingConv = TheCall->getCallingConv();
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switch (CallingConv) {
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default:
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assert(0 && "Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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return LowerCCCCallTo(Op, DAG, CallingConv);
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}
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}
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/// LowerCCCArguments - transform physical registers into virtual registers and
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/// generate load operations for arguments places on the stack.
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// FIXME: struct return stuff
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@ -225,6 +238,166 @@ SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
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}
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/// LowerCCCCallTo - functions arguments are copied from virtual regs to
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/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
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/// TODO: sret.
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SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
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unsigned CC) {
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CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
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SDValue Chain = TheCall->getChain();
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SDValue Callee = TheCall->getCallee();
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bool isVarArg = TheCall->isVarArg();
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DebugLoc dl = Op.getDebugLoc();
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
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CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
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getPointerTy(), true));
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SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
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SmallVector<SDValue, 12> MemOpChains;
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SDValue StackPtr;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// Arguments start after the 5 first operands of ISD::CALL
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SDValue Arg = TheCall->getArg(i);
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: assert(0 && "Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at RegsToPass
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// vector
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc());
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
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SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
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StackPtr,
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DAG.getIntPtrConstant(VA.getLocMemOffset()));
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MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
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PseudoSourceValue::getStack(),
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VA.getLocMemOffset()));
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}
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}
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// Transform all store nodes into one single node because all store nodes are
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// independent of each other.
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token chain and
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// flag operands which copy the outgoing args into registers. The InFlag in
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// necessary since all emited instructions must be stuck together.
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SDValue InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
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RegsToPass[i].second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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// Likewise ExternalSymbol -> TargetExternalSymbol.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
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else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
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// Returns a chain & a flag for retval copy to use.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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if (InFlag.getNode())
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Ops.push_back(InFlag);
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Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Create the CALLSEQ_END node.
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Chain = DAG.getCALLSEQ_END(Chain,
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DAG.getConstant(NumBytes, getPointerTy(), true),
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DAG.getConstant(0, getPointerTy(), true),
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InFlag);
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InFlag = Chain.getValue(1);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
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Op.getResNo());
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}
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/// LowerCallResult - Lower the result values of an ISD::CALL into the
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/// appropriate copies out of appropriate physical registers. This assumes that
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/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
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/// being lowered. Returns a SDNode with the same number of values as the
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/// ISD::CALL.
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SDNode*
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MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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CallSDNode *TheCall,
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unsigned CallingConv,
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SelectionDAG &DAG) {
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bool isVarArg = TheCall->isVarArg();
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DebugLoc dl = TheCall->getDebugLoc();
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
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CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
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SmallVector<SDValue, 8> ResultVals;
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
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RVLocs[i].getValVT(), InFlag).getValue(1);
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InFlag = Chain.getValue(2);
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ResultVals.push_back(Chain.getValue(0));
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}
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ResultVals.push_back(Chain);
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// Merge everything together with a MERGE_VALUES node.
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return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
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&ResultVals[0], ResultVals.size()).getNode();
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}
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SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
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SelectionDAG &DAG) {
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assert(Op.getOpcode() == ISD::SRA && "Only SRA is currently supported.");
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@ -255,4 +428,3 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case MSP430ISD::RRA: return "MSP430ISD::RRA";
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}
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}
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@ -28,7 +28,11 @@ namespace llvm {
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RET_FLAG,
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/// Y = RRA X, rotate right arithmetically
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RRA
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RRA,
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/// CALL/TAILCALL - These operations represent an abstract call
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/// instruction, which includes a bunch of information.
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CALL
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};
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}
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@ -47,9 +51,18 @@ namespace llvm {
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
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SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
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SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
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unsigned CC);
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SDNode* LowerCallResult(SDValue Chain, SDValue InFlag,
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CallSDNode *TheCall,
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unsigned CallingConv, SelectionDAG &DAG);
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private:
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const MSP430Subtarget &Subtarget;
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const MSP430TargetMachine &TM;
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@ -22,6 +22,7 @@ class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
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//===----------------------------------------------------------------------===//
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// Type Profiles.
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//===----------------------------------------------------------------------===//
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def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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//===----------------------------------------------------------------------===//
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// MSP430 Specific Node Definitions.
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@ -31,6 +32,9 @@ def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
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def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
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def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
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[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
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//===----------------------------------------------------------------------===//
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// MSP430 Operand Definitions.
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//===----------------------------------------------------------------------===//
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