mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-16 14:31:59 +00:00
[PowerPC] Fix hi/lo encoding in old-style code emitter
This patch implements the equivalent change to r182091/r182092 in the old-style code emitter. Instead of having two separate 16-bit immediate encoding routines depending on the instruction, this patch introduces a single encoder that checks the machine operand flags to decide whether the low or high half of a symbol address is required. Since now both encoders make no further distinction between "symbolLo" and "symbolHi", the .td operand can now use a single getS16ImmEncoding method. Tested by running the old-style JIT tests on 32-bit Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182097 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
e152eac63e
commit
4456a8ec76
@ -48,10 +48,8 @@ public:
|
||||
SmallVectorImpl<MCFixup> &Fixups) const;
|
||||
unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const;
|
||||
unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const;
|
||||
unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const;
|
||||
unsigned getS16ImmEncoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const;
|
||||
unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const;
|
||||
unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
|
||||
@ -136,18 +134,7 @@ unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo,
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned PPCMCCodeEmitter::getHA16Encoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const {
|
||||
const MCOperand &MO = MI.getOperand(OpNo);
|
||||
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
|
||||
|
||||
// Add a fixup for the branch target.
|
||||
Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
|
||||
(MCFixupKind)PPC::fixup_ppc_half16));
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned PPCMCCodeEmitter::getLO16Encoding(const MCInst &MI, unsigned OpNo,
|
||||
unsigned PPCMCCodeEmitter::getS16ImmEncoding(const MCInst &MI, unsigned OpNo,
|
||||
SmallVectorImpl<MCFixup> &Fixups) const {
|
||||
const MCOperand &MO = MI.getOperand(OpNo);
|
||||
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
|
||||
|
@ -64,8 +64,7 @@ namespace {
|
||||
unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
|
||||
unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
|
||||
|
||||
unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
|
||||
unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
|
||||
unsigned getS16ImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
|
||||
unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
|
||||
unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
|
||||
unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
|
||||
@ -194,21 +193,19 @@ unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned PPCCodeEmitter::getHA16Encoding(const MachineInstr &MI,
|
||||
unsigned OpNo) const {
|
||||
unsigned PPCCodeEmitter::getS16ImmEncoding(const MachineInstr &MI,
|
||||
unsigned OpNo) const {
|
||||
const MachineOperand &MO = MI.getOperand(OpNo);
|
||||
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
|
||||
|
||||
MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_high));
|
||||
return 0;
|
||||
}
|
||||
unsigned RelocID;
|
||||
switch (MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) {
|
||||
default: llvm_unreachable("Unsupported target operand flags!");
|
||||
case PPCII::MO_HA16: RelocID = PPC::reloc_absolute_high; break;
|
||||
case PPCII::MO_LO16: RelocID = PPC::reloc_absolute_low; break;
|
||||
}
|
||||
|
||||
unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI,
|
||||
unsigned OpNo) const {
|
||||
const MachineOperand &MO = MI.getOperand(OpNo);
|
||||
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
|
||||
|
||||
MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
|
||||
MCE.addRelocation(GetRelocation(MO, RelocID));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -25,12 +25,12 @@ def u16imm64 : Operand<i64> {
|
||||
}
|
||||
def symbolHi64 : Operand<i64> {
|
||||
let PrintMethod = "printSymbolHi";
|
||||
let EncoderMethod = "getHA16Encoding";
|
||||
let EncoderMethod = "getS16ImmEncoding";
|
||||
let ParserMatchClass = PPCS16ImmAsmOperand;
|
||||
}
|
||||
def symbolLo64 : Operand<i64> {
|
||||
let PrintMethod = "printSymbolLo";
|
||||
let EncoderMethod = "getLO16Encoding";
|
||||
let EncoderMethod = "getS16ImmEncoding";
|
||||
let ParserMatchClass = PPCS16ImmAsmOperand;
|
||||
}
|
||||
def tocentry : Operand<iPTR> {
|
||||
|
@ -458,12 +458,12 @@ def aaddr : Operand<iPTR> {
|
||||
}
|
||||
def symbolHi: Operand<i32> {
|
||||
let PrintMethod = "printSymbolHi";
|
||||
let EncoderMethod = "getHA16Encoding";
|
||||
let EncoderMethod = "getS16ImmEncoding";
|
||||
let ParserMatchClass = PPCS16ImmAsmOperand;
|
||||
}
|
||||
def symbolLo: Operand<i32> {
|
||||
let PrintMethod = "printSymbolLo";
|
||||
let EncoderMethod = "getLO16Encoding";
|
||||
let EncoderMethod = "getS16ImmEncoding";
|
||||
let ParserMatchClass = PPCS16ImmAsmOperand;
|
||||
}
|
||||
def PPCCRBitMaskOperand : AsmOperandClass {
|
||||
|
Loading…
x
Reference in New Issue
Block a user