6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-10 02:25:47 +00:00
Code Issues Projects Releases Wiki Activity

Reverting r55190, r55191, and r55192. They broke the build with this error message:

Browse Source 
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55200 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
2008-08-22 20:51:05 +00:00
parent 5ed3cbb753
commit 449416deb6
5 changed files with 26 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/FastISel.h
View File

@@ -17,7 +17,6 @@
#include "llvm/BasicBlock.h" #include "llvm/BasicBlock.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/SelectionDAGNodes.h"
#include <map>
namespace llvm { namespace llvm {
@@ -53,7 +52,6 @@ public:
BasicBlock::iterator BasicBlock::iterator
SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End, SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
DenseMap<const Value*, unsigned> &ValueMap, DenseMap<const Value*, unsigned> &ValueMap,
std::map<const BasicBlock*, MachineBasicBlock *> &MBBMap,
MachineBasicBlock *MBB); MachineBasicBlock *MBB);
virtual ~FastISel(); virtual ~FastISel();

23
lib/CodeGen/SelectionDAG/FastISel.cpp
View File

@@ -145,8 +145,6 @@ BasicBlock::iterator
FastISel::SelectInstructions(BasicBlock::iterator Begin, FastISel::SelectInstructions(BasicBlock::iterator Begin,
BasicBlock::iterator End, BasicBlock::iterator End,
DenseMap<const Value*, unsigned> &ValueMap, DenseMap<const Value*, unsigned> &ValueMap,
std::map<const BasicBlock*,
MachineBasicBlock *> &MBBMap,
MachineBasicBlock *mbb) { MachineBasicBlock *mbb) {
MBB = mbb; MBB = mbb;
BasicBlock::iterator I = Begin; BasicBlock::iterator I = Begin;
@@ -197,24 +195,19 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
case Instruction::Br: { case Instruction::Br: {
BranchInst *BI = cast<BranchInst>(I); BranchInst *BI = cast<BranchInst>(I);
// For now, check for and handle just the most trivial case: an
// unconditional fall-through branch.
if (BI->isUnconditional()) { if (BI->isUnconditional()) {
MachineFunction::iterator NextMBB = MachineFunction::iterator NextMBB =
next(MachineFunction::iterator(MBB)); next(MachineFunction::iterator(MBB));
BasicBlock *LLVMSucc = BI->getSuccessor(0); if (NextMBB != MF.end() &&
MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; NextMBB->getBasicBlock() == BI->getSuccessor(0)) {
MBB->addSuccessor(NextMBB);
if (NextMBB != MF.end() && MSucc == NextMBB) { break;
// The unconditional fall-through case, which needs no instructions.
} else {
// The unconditional branch case.
TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
} }
MBB->addSuccessor(MSucc);
break;
} }
// Conditional branches are not handed yet. // Something more complicated. Halt "fast" selection and bail.
// Halt "fast" selection and bail.
return I; return I;
} }

2
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@@ -5113,7 +5113,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
cast<BranchInst>(LLVMBB->getTerminator())->isUnconditional()) { cast<BranchInst>(LLVMBB->getTerminator())->isUnconditional()) {
if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) { if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
Begin = F->SelectInstructions(Begin, LLVMBB->end(), Begin = F->SelectInstructions(Begin, LLVMBB->end(),
FuncInfo.ValueMap, FuncInfo.MBBMap, BB); FuncInfo.ValueMap, BB);
// Clean up the FastISel object. TODO: Reorganize what data is // Clean up the FastISel object. TODO: Reorganize what data is
// stored in the FastISel class itself and what is merely passed // stored in the FastISel class itself and what is merely passed

12
lib/Target/X86/X86Instr64bit.td
View File

@@ -1254,9 +1254,15 @@ def : Pat<(i64 (zext GR32:$src)),
def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
// extload // extload
def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; def : Pat<(extloadi64i1 addr:$src),
def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src),
def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; x86_subreg_8bit)>;
def : Pat<(extloadi64i8 addr:$src),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src),
x86_subreg_8bit)>;
def : Pat<(extloadi64i16 addr:$src),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV16rm addr:$src),
x86_subreg_16bit)>;
def : Pat<(extloadi64i32 addr:$src), def : Pat<(extloadi64i32 addr:$src),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src),
x86_subreg_32bit)>; x86_subreg_32bit)>;

21
lib/Target/X86/X86InstrInfo.td
View File

@@ -2784,24 +2784,19 @@ def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
// extload bool -> extload byte // extload bool -> extload byte
def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
def : Pat<(extloadi16i1 addr:$src), def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
(INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src), Requires<[In32BitMode]>;
x86_subreg_8bit)>;
def : Pat<(extloadi16i8 addr:$src),
(INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src),
x86_subreg_8bit)>;
// For extloads with 32-bit results, chose instructions that
// define the whole 32 bits of the result, to avoid partial-register
// updates.
def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
Requires<[In32BitMode]>;
def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
// anyext // anyext
def : Pat<(i16 (anyext GR8:$src)), def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
(INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>; Requires<[In32BitMode]>;
def : Pat<(i32 (anyext GR8:$src)), def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>; Requires<[In32BitMode]>;
def : Pat<(i32 (anyext GR16:$src)), def : Pat<(i32 (anyext GR16:$src)),
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>; (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;