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Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2008-08-14 22:49:33 +00:00
parent c0573b13a1
commit 44eb65cf58
21 changed files with 95 additions and 88 deletions
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15
include/llvm/Target/TargetInstrInfo.h
View File

@@ -195,7 +195,7 @@ public:
/// ///
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const { SmallVectorImpl<MachineOperand> &Cond) const {
return true; return true;
} }
@@ -215,7 +215,7 @@ public:
/// instructions inserted. /// instructions inserted.
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond) const {
assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
return 0; return 0;
} }
@@ -342,7 +342,8 @@ public:
/// ReverseBranchCondition - Reverses the branch condition of the specified /// ReverseBranchCondition - Reverses the branch condition of the specified
/// condition list, returning false on success and true if it cannot be /// condition list, returning false on success and true if it cannot be
/// reversed. /// reversed.
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
return true; return true;
} }
@@ -368,13 +369,13 @@ public:
/// instruction. It returns true if the operation was successful. /// instruction. It returns true if the operation was successful.
virtual virtual
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const = 0; const SmallVectorImpl<MachineOperand> &Pred) const = 0;
/// SubsumesPredicate - Returns true if the first specified predicate /// SubsumesPredicate - Returns true if the first specified predicate
/// subsumes the second, e.g. GE subsumes GT. /// subsumes the second, e.g. GE subsumes GT.
virtual virtual
bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const std::vector<MachineOperand> &Pred2) const { const SmallVectorImpl<MachineOperand> &Pred2) const {
return false; return false;
} }
@@ -421,7 +422,7 @@ public:
virtual bool CommuteChangesDestination(MachineInstr *MI, virtual bool CommuteChangesDestination(MachineInstr *MI,
unsigned &OpIdx) const; unsigned &OpIdx) const;
virtual bool PredicateInstruction(MachineInstr *MI, virtual bool PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const; const SmallVectorImpl<MachineOperand> &Pred) const;
virtual void reMaterialize(MachineBasicBlock &MBB, virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned DestReg,

28
lib/CodeGen/BranchFolding.cpp
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@@ -95,7 +95,7 @@ namespace {
bool CanFallThrough(MachineBasicBlock *CurBB); bool CanFallThrough(MachineBasicBlock *CurBB);
bool CanFallThrough(MachineBasicBlock *CurBB, bool BranchUnAnalyzable, bool CanFallThrough(MachineBasicBlock *CurBB, bool BranchUnAnalyzable,
MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond); const SmallVectorImpl<MachineOperand> &Cond);
}; };
char BranchFolder::ID = 0; char BranchFolder::ID = 0;
} }
@@ -190,7 +190,7 @@ bool BranchFolder::runOnMachineFunction(MachineFunction &MF) {
bool EverMadeChange = false; bool EverMadeChange = false;
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; I++) { for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; I++) {
MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0; MachineBasicBlock *MBB = I, *TBB = 0, *FBB = 0;
std::vector<MachineOperand> Cond; SmallVector<MachineOperand, 4> Cond;
if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond)) if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond))
EverMadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); EverMadeChange |= MBB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
EverMadeChange |= OptimizeImpDefsBlock(MBB); EverMadeChange |= OptimizeImpDefsBlock(MBB);
@@ -364,7 +364,7 @@ void BranchFolder::ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
// If OldBB isn't immediately before OldBB, insert a branch to it. // If OldBB isn't immediately before OldBB, insert a branch to it.
if (++MachineFunction::iterator(OldBB) != MachineFunction::iterator(NewDest)) if (++MachineFunction::iterator(OldBB) != MachineFunction::iterator(NewDest))
TII->InsertBranch(*OldBB, NewDest, 0, std::vector<MachineOperand>()); TII->InsertBranch(*OldBB, NewDest, 0, SmallVector<MachineOperand, 1>());
OldBB->addSuccessor(NewDest); OldBB->addSuccessor(NewDest);
++NumTailMerge; ++NumTailMerge;
} }
@@ -432,7 +432,7 @@ static void FixTail(MachineBasicBlock* CurMBB, MachineBasicBlock *SuccBB,
MachineFunction *MF = CurMBB->getParent(); MachineFunction *MF = CurMBB->getParent();
MachineFunction::iterator I = next(MachineFunction::iterator(CurMBB)); MachineFunction::iterator I = next(MachineFunction::iterator(CurMBB));
MachineBasicBlock *TBB = 0, *FBB = 0; MachineBasicBlock *TBB = 0, *FBB = 0;
std::vector<MachineOperand> Cond; SmallVector<MachineOperand, 4> Cond;
if (I != MF->end() && if (I != MF->end() &&
!TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond)) { !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond)) {
MachineBasicBlock *NextBB = I; MachineBasicBlock *NextBB = I;
@@ -444,7 +444,7 @@ static void FixTail(MachineBasicBlock* CurMBB, MachineBasicBlock *SuccBB,
} }
} }
} }
TII->InsertBranch(*CurMBB, SuccBB, NULL, std::vector<MachineOperand>()); TII->InsertBranch(*CurMBB, SuccBB, NULL, SmallVector<MachineOperand, 1>());
} }
static bool MergeCompare(const std::pair<unsigned,MachineBasicBlock*> &p, static bool MergeCompare(const std::pair<unsigned,MachineBasicBlock*> &p,
@@ -710,11 +710,11 @@ bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
if (PBB==IBB) if (PBB==IBB)
continue; continue;
MachineBasicBlock *TBB = 0, *FBB = 0; MachineBasicBlock *TBB = 0, *FBB = 0;
std::vector<MachineOperand> Cond; SmallVector<MachineOperand, 4> Cond;
if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond)) { if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond)) {
// Failing case: IBB is the target of a cbr, and // Failing case: IBB is the target of a cbr, and
// we cannot reverse the branch. // we cannot reverse the branch.
std::vector<MachineOperand> NewCond(Cond); SmallVector<MachineOperand, 4> NewCond(Cond);
if (!Cond.empty() && TBB==IBB) { if (!Cond.empty() && TBB==IBB) {
if (TII->ReverseBranchCondition(NewCond)) if (TII->ReverseBranchCondition(NewCond))
continue; continue;
@@ -803,7 +803,7 @@ bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB,
bool BranchUnAnalyzable, bool BranchUnAnalyzable,
MachineBasicBlock *TBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) { const SmallVectorImpl<MachineOperand> &Cond) {
MachineFunction::iterator Fallthrough = CurBB; MachineFunction::iterator Fallthrough = CurBB;
++Fallthrough; ++Fallthrough;
// If FallthroughBlock is off the end of the function, it can't fall through. // If FallthroughBlock is off the end of the function, it can't fall through.
@@ -844,7 +844,7 @@ bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB,
/// ///
bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB) { bool BranchFolder::CanFallThrough(MachineBasicBlock *CurBB) {
MachineBasicBlock *TBB = 0, *FBB = 0; MachineBasicBlock *TBB = 0, *FBB = 0;
std::vector<MachineOperand> Cond; SmallVector<MachineOperand, 4> Cond;
bool CurUnAnalyzable = TII->AnalyzeBranch(*CurBB, TBB, FBB, Cond); bool CurUnAnalyzable = TII->AnalyzeBranch(*CurBB, TBB, FBB, Cond);
return CanFallThrough(CurBB, CurUnAnalyzable, TBB, FBB, Cond); return CanFallThrough(CurBB, CurUnAnalyzable, TBB, FBB, Cond);
} }
@@ -908,7 +908,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
MachineBasicBlock &PrevBB = *prior(MachineFunction::iterator(MBB)); MachineBasicBlock &PrevBB = *prior(MachineFunction::iterator(MBB));
MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0; MachineBasicBlock *PriorTBB = 0, *PriorFBB = 0;
std::vector<MachineOperand> PriorCond; SmallVector<MachineOperand, 4> PriorCond;
bool PriorUnAnalyzable = bool PriorUnAnalyzable =
TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond); TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond);
if (!PriorUnAnalyzable) { if (!PriorUnAnalyzable) {
@@ -952,7 +952,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
// if the branch condition is reversible, reverse the branch to create a // if the branch condition is reversible, reverse the branch to create a
// fall-through. // fall-through.
if (PriorTBB == MBB) { if (PriorTBB == MBB) {
std::vector<MachineOperand> NewPriorCond(PriorCond); SmallVector<MachineOperand, 4> NewPriorCond(PriorCond);
if (!TII->ReverseBranchCondition(NewPriorCond)) { if (!TII->ReverseBranchCondition(NewPriorCond)) {
TII->RemoveBranch(PrevBB); TII->RemoveBranch(PrevBB);
TII->InsertBranch(PrevBB, PriorFBB, 0, NewPriorCond); TII->InsertBranch(PrevBB, PriorFBB, 0, NewPriorCond);
@@ -1002,7 +1002,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
if (DoTransform) { if (DoTransform) {
// Reverse the branch so we will fall through on the previous true cond. // Reverse the branch so we will fall through on the previous true cond.
std::vector<MachineOperand> NewPriorCond(PriorCond); SmallVector<MachineOperand, 4> NewPriorCond(PriorCond);
if (!TII->ReverseBranchCondition(NewPriorCond)) { if (!TII->ReverseBranchCondition(NewPriorCond)) {
DOUT << "\nMoving MBB: " << *MBB; DOUT << "\nMoving MBB: " << *MBB;
DOUT << "To make fallthrough to: " << *PriorTBB << "\n"; DOUT << "To make fallthrough to: " << *PriorTBB << "\n";
@@ -1022,7 +1022,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
// Analyze the branch in the current block. // Analyze the branch in the current block.
MachineBasicBlock *CurTBB = 0, *CurFBB = 0; MachineBasicBlock *CurTBB = 0, *CurFBB = 0;
std::vector<MachineOperand> CurCond; SmallVector<MachineOperand, 4> CurCond;
bool CurUnAnalyzable = TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond); bool CurUnAnalyzable = TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond);
if (!CurUnAnalyzable) { if (!CurUnAnalyzable) {
// If the CFG for the prior block has extra edges, remove them. // If the CFG for the prior block has extra edges, remove them.
@@ -1034,7 +1034,7 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
// we want: // we want:
// Loop: xxx; jncc Loop; jmp Out // Loop: xxx; jncc Loop; jmp Out
if (CurTBB && CurFBB && CurFBB == MBB && CurTBB != MBB) { if (CurTBB && CurFBB && CurFBB == MBB && CurTBB != MBB) {
std::vector<MachineOperand> NewCond(CurCond); SmallVector<MachineOperand, 4> NewCond(CurCond);
if (!TII->ReverseBranchCondition(NewCond)) { if (!TII->ReverseBranchCondition(NewCond)) {
TII->RemoveBranch(*MBB); TII->RemoveBranch(*MBB);
TII->InsertBranch(*MBB, CurFBB, CurTBB, NewCond); TII->InsertBranch(*MBB, CurFBB, CurTBB, NewCond);

39
lib/CodeGen/IfConversion.cpp
View File

@@ -103,8 +103,8 @@ namespace {
MachineBasicBlock *BB; MachineBasicBlock *BB;
MachineBasicBlock *TrueBB; MachineBasicBlock *TrueBB;
MachineBasicBlock *FalseBB; MachineBasicBlock *FalseBB;
std::vector<MachineOperand> BrCond; SmallVector<MachineOperand, 4> BrCond;
std::vector<MachineOperand> Predicate; SmallVector<MachineOperand, 4> Predicate;
BBInfo() : IsDone(false), IsBeingAnalyzed(false), BBInfo() : IsDone(false), IsBeingAnalyzed(false),
IsAnalyzed(false), IsEnqueued(false), IsBrAnalyzable(false), IsAnalyzed(false), IsEnqueued(false), IsBrAnalyzable(false),
HasFallThrough(false), IsUnpredicable(false), HasFallThrough(false), IsUnpredicable(false),
@@ -161,7 +161,7 @@ namespace {
void ScanInstructions(BBInfo &BBI); void ScanInstructions(BBInfo &BBI);
BBInfo &AnalyzeBlock(MachineBasicBlock *BB, BBInfo &AnalyzeBlock(MachineBasicBlock *BB,
std::vector<IfcvtToken*> &Tokens); std::vector<IfcvtToken*> &Tokens);
bool FeasibilityAnalysis(BBInfo &BBI, std::vector<MachineOperand> &Cond, bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Cond,
bool isTriangle = false, bool RevBranch = false); bool isTriangle = false, bool RevBranch = false);
bool AnalyzeBlocks(MachineFunction &MF, bool AnalyzeBlocks(MachineFunction &MF,
std::vector<IfcvtToken*> &Tokens); std::vector<IfcvtToken*> &Tokens);
@@ -173,9 +173,9 @@ namespace {
unsigned NumDups1, unsigned NumDups2); unsigned NumDups1, unsigned NumDups2);
void PredicateBlock(BBInfo &BBI, void PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E, MachineBasicBlock::iterator E,
std::vector<MachineOperand> &Cond); SmallVectorImpl<MachineOperand> &Cond);
void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI, void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
std::vector<MachineOperand> &Cond, SmallVectorImpl<MachineOperand> &Cond,
bool IgnoreBr = false); bool IgnoreBr = false);
void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI); void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI);
@@ -604,7 +604,7 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
/// FeasibilityAnalysis - Determine if the block is a suitable candidate to be /// FeasibilityAnalysis - Determine if the block is a suitable candidate to be
/// predicated by the specified predicate. /// predicated by the specified predicate.
bool IfConverter::FeasibilityAnalysis(BBInfo &BBI, bool IfConverter::FeasibilityAnalysis(BBInfo &BBI,
std::vector<MachineOperand> &Pred, SmallVectorImpl<MachineOperand> &Pred,
bool isTriangle, bool RevBranch) { bool isTriangle, bool RevBranch) {
// If the block is dead or unpredicable, then it cannot be predicated. // If the block is dead or unpredicable, then it cannot be predicated.
if (BBI.IsDone || BBI.IsUnpredicable) if (BBI.IsDone || BBI.IsUnpredicable)
@@ -620,8 +620,8 @@ bool IfConverter::FeasibilityAnalysis(BBInfo &BBI,
return false; return false;
// Test predicate subsumsion. // Test predicate subsumsion.
std::vector<MachineOperand> RevPred(Pred); SmallVector<MachineOperand, 4> RevPred(Pred.begin(), Pred.end());
std::vector<MachineOperand> Cond(BBI.BrCond); SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (RevBranch) { if (RevBranch) {
if (TII->ReverseBranchCondition(Cond)) if (TII->ReverseBranchCondition(Cond))
return false; return false;
@@ -672,7 +672,7 @@ IfConverter::BBInfo &IfConverter::AnalyzeBlock(MachineBasicBlock *BB,
return BBI; return BBI;
} }
std::vector<MachineOperand> RevCond(BBI.BrCond); SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
bool CanRevCond = !TII->ReverseBranchCondition(RevCond); bool CanRevCond = !TII->ReverseBranchCondition(RevCond);
unsigned Dups = 0; unsigned Dups = 0;
@@ -815,7 +815,7 @@ void IfConverter::InvalidatePreds(MachineBasicBlock *BB) {
/// ///
static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB, static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB,
const TargetInstrInfo *TII) { const TargetInstrInfo *TII) {
std::vector<MachineOperand> NoCond; SmallVector<MachineOperand, 1> NoCond;
TII->InsertBranch(*BB, ToBB, NULL, NoCond); TII->InsertBranch(*BB, ToBB, NULL, NoCond);
} }
@@ -823,7 +823,7 @@ static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB,
/// successors. /// successors.
void IfConverter::RemoveExtraEdges(BBInfo &BBI) { void IfConverter::RemoveExtraEdges(BBInfo &BBI) {
MachineBasicBlock *TBB = NULL, *FBB = NULL; MachineBasicBlock *TBB = NULL, *FBB = NULL;
std::vector<MachineOperand> Cond; SmallVector<MachineOperand, 4> Cond;
if (!TII->AnalyzeBranch(*BBI.BB, TBB, FBB, Cond)) if (!TII->AnalyzeBranch(*BBI.BB, TBB, FBB, Cond))
BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
} }
@@ -836,7 +836,7 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
BBInfo *CvtBBI = &TrueBBI; BBInfo *CvtBBI = &TrueBBI;
BBInfo *NextBBI = &FalseBBI; BBInfo *NextBBI = &FalseBBI;
std::vector<MachineOperand> Cond(BBI.BrCond); SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (Kind == ICSimpleFalse) if (Kind == ICSimpleFalse)
std::swap(CvtBBI, NextBBI); std::swap(CvtBBI, NextBBI);
@@ -901,7 +901,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
BBInfo *CvtBBI = &TrueBBI; BBInfo *CvtBBI = &TrueBBI;
BBInfo *NextBBI = &FalseBBI; BBInfo *NextBBI = &FalseBBI;
std::vector<MachineOperand> Cond(BBI.BrCond); SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (Kind == ICTriangleFalse || Kind == ICTriangleFRev) if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
std::swap(CvtBBI, NextBBI); std::swap(CvtBBI, NextBBI);
@@ -954,7 +954,8 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
// If 'true' block has a 'false' successor, add an exit branch to it. // If 'true' block has a 'false' successor, add an exit branch to it.
if (HasEarlyExit) { if (HasEarlyExit) {
std::vector<MachineOperand> RevCond(CvtBBI->BrCond); SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
CvtBBI->BrCond.end());
if (TII->ReverseBranchCondition(RevCond)) if (TII->ReverseBranchCondition(RevCond))
assert(false && "Unable to reverse branch condition!"); assert(false && "Unable to reverse branch condition!");
TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond); TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond);
@@ -1026,10 +1027,10 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
// block would clobber the predicate, in that case, do the opposite. // block would clobber the predicate, in that case, do the opposite.
BBInfo *BBI1 = &TrueBBI; BBInfo *BBI1 = &TrueBBI;
BBInfo *BBI2 = &FalseBBI; BBInfo *BBI2 = &FalseBBI;
std::vector<MachineOperand> RevCond(BBI.BrCond); SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
TII->ReverseBranchCondition(RevCond); TII->ReverseBranchCondition(RevCond);
std::vector<MachineOperand> *Cond1 = &BBI.BrCond; SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;
std::vector<MachineOperand> *Cond2 = &RevCond; SmallVector<MachineOperand, 4> *Cond2 = &RevCond;
// Figure out the more profitable ordering. // Figure out the more profitable ordering.
bool DoSwap = false; bool DoSwap = false;
@@ -1111,7 +1112,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
/// specified end with the specified condition. /// specified end with the specified condition.
void IfConverter::PredicateBlock(BBInfo &BBI, void IfConverter::PredicateBlock(BBInfo &BBI,
MachineBasicBlock::iterator E, MachineBasicBlock::iterator E,
std::vector<MachineOperand> &Cond) { SmallVectorImpl<MachineOperand> &Cond) {
for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) { for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
if (TII->isPredicated(I)) if (TII->isPredicated(I))
continue; continue;
@@ -1132,7 +1133,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
/// CopyAndPredicateBlock - Copy and predicate instructions from source BB to /// CopyAndPredicateBlock - Copy and predicate instructions from source BB to
/// the destination block. Skip end of block branches if IgnoreBr is true. /// the destination block. Skip end of block branches if IgnoreBr is true.
void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI, void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
std::vector<MachineOperand> &Cond, SmallVectorImpl<MachineOperand> &Cond,
bool IgnoreBr) { bool IgnoreBr) {
MachineFunction &MF = *ToBBI.BB->getParent(); MachineFunction &MF = *ToBBI.BB->getParent();

2
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@@ -631,7 +631,7 @@ static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
if (MBB == SuccMBB) if (MBB == SuccMBB)
return true; return true;
MachineBasicBlock *TBB = 0, *FBB = 0; MachineBasicBlock *TBB = 0, *FBB = 0;
std::vector<MachineOperand> Cond; SmallVector<MachineOperand, 4> Cond;
return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB && return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
MBB->isSuccessor(SuccMBB); MBB->isSuccessor(SuccMBB);
} }

3
lib/CodeGen/TargetInstrInfoImpl.cpp
View File

@@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
using namespace llvm; using namespace llvm;
@@ -77,7 +78,7 @@ bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI,
bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const { const SmallVectorImpl<MachineOperand> &Pred) const {
bool MadeChange = false; bool MadeChange = false;
const TargetInstrDesc &TID = MI->getDesc(); const TargetInstrDesc &TID = MI->getDesc();
if (!TID.isPredicable()) if (!TID.isPredicable())

12
lib/Target/ARM/ARMInstrInfo.cpp
View File

@@ -333,7 +333,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
// Branch analysis. // Branch analysis.
bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const { SmallVectorImpl<MachineOperand> &Cond) const {
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
@@ -432,7 +432,7 @@ unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond) const {
MachineFunction &MF = *MBB.getParent(); MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B; int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
@@ -799,7 +799,7 @@ bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
} }
bool ARMInstrInfo:: bool ARMInstrInfo::
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
Cond[0].setImm(ARMCC::getOppositeCondition(CC)); Cond[0].setImm(ARMCC::getOppositeCondition(CC));
return false; return false;
@@ -811,7 +811,7 @@ bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
} }
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI, bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const { const SmallVectorImpl<MachineOperand> &Pred) const {
unsigned Opc = MI->getOpcode(); unsigned Opc = MI->getOpcode();
if (Opc == ARM::B || Opc == ARM::tB) { if (Opc == ARM::B || Opc == ARM::tB) {
MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc)); MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
@@ -831,8 +831,8 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
} }
bool bool
ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1, ARMInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const std::vector<MachineOperand> &Pred2) const{ const SmallVectorImpl<MachineOperand> &Pred2) const{
if (Pred1.size() > 2 || Pred2.size() > 2) if (Pred1.size() > 2 || Pred2.size() > 2)
return false; return false;

13
lib/Target/ARM/ARMInstrInfo.h
View File

@@ -158,11 +158,11 @@ public:
// Branch analysis. // Branch analysis.
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const; SmallVectorImpl<MachineOperand> &Cond) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB, virtual void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
@@ -210,18 +210,19 @@ public:
SmallVectorImpl<unsigned> &Ops) const; SmallVectorImpl<unsigned> &Ops) const;
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
// Predication support. // Predication support.
virtual bool isPredicated(const MachineInstr *MI) const; virtual bool isPredicated(const MachineInstr *MI) const;
virtual virtual
bool PredicateInstruction(MachineInstr *MI, bool PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const; const SmallVectorImpl<MachineOperand> &Pred) const;
virtual virtual
bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const std::vector<MachineOperand> &Pred2) const; const SmallVectorImpl<MachineOperand> &Pred2) const;
virtual bool DefinesPredicate(MachineInstr *MI, virtual bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const; std::vector<MachineOperand> &Pred) const;

11
lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@@ -100,9 +100,10 @@ static bool isAlphaIntCondCode(unsigned Opcode) {
} }
} }
unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *FBB, MachineBasicBlock *TBB,
const std::vector<MachineOperand> &Cond)const{ MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond) const {
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 2 || Cond.size() == 0) &&
"Alpha branch conditions have two components!"); "Alpha branch conditions have two components!");
@@ -315,7 +316,7 @@ static unsigned AlphaRevCondCode(unsigned Opcode) {
// Branch analysis. // Branch analysis.
bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const { SmallVectorImpl<MachineOperand> &Cond) const {
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
@@ -418,7 +419,7 @@ bool AlphaInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
} }
} }
bool AlphaInstrInfo:: bool AlphaInstrInfo::
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
assert(Cond.size() == 2 && "Invalid Alpha branch opcode!"); assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm())); Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
return false; return false;

6
lib/Target/Alpha/AlphaInstrInfo.h
View File

@@ -41,7 +41,7 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB, virtual void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
@@ -81,12 +81,12 @@ public:
bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const; SmallVectorImpl<MachineOperand> &Cond) const;
unsigned RemoveBranch(MachineBasicBlock &MBB) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const;
void insertNoop(MachineBasicBlock &MBB, void insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const; MachineBasicBlock::iterator MI) const;
bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
}; };
} }

2
lib/Target/IA64/IA64InstrInfo.cpp
View File

@@ -50,7 +50,7 @@ bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned unsigned
IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond)const { const SmallVectorImpl<MachineOperand> &Cond)const {
// Can only insert uncond branches so far. // Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB); BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);

2
lib/Target/IA64/IA64InstrInfo.h
View File

@@ -39,7 +39,7 @@ public:
unsigned& destReg) const; unsigned& destReg) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB, virtual void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,

9
lib/Target/Mips/MipsInstrInfo.cpp
View File

@@ -446,7 +446,7 @@ Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const SmallVectorImpl<MachineOperand> &Cond) const
{ {
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
@@ -528,9 +528,8 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
unsigned MipsInstrInfo:: unsigned MipsInstrInfo::
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, const std::vector<MachineOperand> &Cond) MachineBasicBlock *FBB,
const const SmallVectorImpl<MachineOperand> &Cond) const {
{
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
@@ -615,7 +614,7 @@ BlockHasNoFallThrough(MachineBasicBlock &MBB) const
/// ReverseBranchCondition - Return the inverse opcode of the /// ReverseBranchCondition - Return the inverse opcode of the
/// specified Branch instruction. /// specified Branch instruction.
bool MipsInstrInfo:: bool MipsInstrInfo::
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
{ {
assert( (Cond.size() == 3 || Cond.size() == 2) && assert( (Cond.size() == 3 || Cond.size() == 2) &&
"Invalid Mips branch condition!"); "Invalid Mips branch condition!");

7
lib/Target/Mips/MipsInstrInfo.h
View File

@@ -164,11 +164,11 @@ public:
/// Branch Analysis /// Branch Analysis
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const; SmallVectorImpl<MachineOperand> &Cond) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB, virtual void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
@@ -207,7 +207,8 @@ public:
} }
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
/// Insert nop instruction when hazard condition is found /// Insert nop instruction when hazard condition is found
virtual void insertNoop(MachineBasicBlock &MBB, virtual void insertNoop(MachineBasicBlock &MBB,

2
lib/Target/PIC16/PIC16InstrInfo.cpp
View File

@@ -121,7 +121,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned PIC16InstrInfo:: unsigned PIC16InstrInfo::
InsertBranch(MachineBasicBlock &MBB, InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const const SmallVectorImpl<MachineOperand> &Cond) const
{ {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");

2
lib/Target/PIC16/PIC16InstrInfo.h
View File

@@ -69,7 +69,7 @@ public:
/// instructions inserted. /// instructions inserted.
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const ; const SmallVectorImpl<MachineOperand> &Cond) const ;
}; };

6
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@@ -210,7 +210,7 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
// Branch analysis. // Branch analysis.
bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const { SmallVectorImpl<MachineOperand> &Cond) const {
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
@@ -292,7 +292,7 @@ unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
unsigned unsigned
PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) && assert((Cond.size() == 2 || Cond.size() == 0) &&
@@ -762,7 +762,7 @@ bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
} }
bool PPCInstrInfo:: bool PPCInstrInfo::
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
assert(Cond.size() == 2 && "Invalid PPC branch opcode!"); assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
// Leave the CR# the same, but invert the condition. // Leave the CR# the same, but invert the condition.
Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));

7
lib/Target/PowerPC/PPCInstrInfo.h
View File

@@ -107,11 +107,11 @@ public:
// Branch analysis. // Branch analysis.
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const; SmallVectorImpl<MachineOperand> &Cond) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB, virtual void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
@@ -156,7 +156,8 @@ public:
SmallVectorImpl<unsigned> &Ops) const; SmallVectorImpl<unsigned> &Ops) const;
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
/// GetInstSize - Return the number of bytes of code the specified /// GetInstSize - Return the number of bytes of code the specified
/// instruction may be. This returns the maximum number of bytes. /// instruction may be. This returns the maximum number of bytes.

2
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@@ -102,7 +102,7 @@ unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI,
unsigned unsigned
SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond)const{ const SmallVectorImpl<MachineOperand> &Cond)const{
// Can only insert uncond branches so far. // Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
BuildMI(&MBB, get(SP::BA)).addMBB(TBB); BuildMI(&MBB, get(SP::BA)).addMBB(TBB);

2
lib/Target/Sparc/SparcInstrInfo.h
View File

@@ -66,7 +66,7 @@ public:
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB, virtual void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,

6
lib/Target/X86/X86InstrInfo.cpp
View File

@@ -1456,7 +1456,7 @@ static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const { SmallVectorImpl<MachineOperand> &Cond) const {
// If the block has no terminators, it just falls into the block after it. // If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end(); MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
@@ -1567,7 +1567,7 @@ static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
unsigned unsigned
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const { const SmallVectorImpl<MachineOperand> &Cond) const {
// Shouldn't be a fall through. // Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 1 || Cond.size() == 0) && assert((Cond.size() == 1 || Cond.size() == 0) &&
@@ -2365,7 +2365,7 @@ bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
} }
bool X86InstrInfo:: bool X86InstrInfo::
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
assert(Cond.size() == 1 && "Invalid X86 branch condition!"); assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm())); Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
return false; return false;

7
lib/Target/X86/X86InstrInfo.h
View File

@@ -306,11 +306,11 @@ public:
virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const; SmallVectorImpl<MachineOperand> &Cond) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const std::vector<MachineOperand> &Cond) const; const SmallVectorImpl<MachineOperand> &Cond) const;
virtual void copyRegToReg(MachineBasicBlock &MBB, virtual void copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
@@ -385,7 +385,8 @@ public:
bool UnfoldLoad, bool UnfoldStore) const; bool UnfoldLoad, bool UnfoldStore) const;
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const; virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const; virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
const TargetRegisterClass *getPointerRegClass() const; const TargetRegisterClass *getPointerRegClass() const;