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fix spello
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27053 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -232,7 +232,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
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case ISD::CopyToReg: {
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case ISD::CopyToReg: {
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unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
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unsigned InReg = getVR(Node->getOperand(2), VRBaseMap);
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unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
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if (InReg != DestReg) // Coallesced away the copy?
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if (InReg != DestReg) // Coalesced away the copy?
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MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
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MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg,
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RegMap->getRegClass(InReg));
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RegMap->getRegClass(InReg));
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break;
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break;
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