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https://github.com/c64scene-ar/llvm-6502.git
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Implement a couple improvements:
Remove dead code in ISD::Constant handling Add support for add long, imm16 We now codegen 'long long foo(long long a) { return ++a; }' as: addic r4, r4, 1 addze r3, r3 blr instead of: li r2, 1 li r5, 0 addc r2, r4, r2 adde r3, r3, r5 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22811 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1436,16 +1436,36 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::SUB_PARTS: {
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assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
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"Not an i64 add/sub!");
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// Emit all of the operands.
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std::vector<unsigned> InVals;
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for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
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InVals.push_back(SelectExpr(N.getOperand(i)));
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unsigned Tmp4 = 0;
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bool ME = isIntImmediate(N.getOperand(3),Tmp3) && ((signed)Tmp3 == -1);
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bool ZE = isIntImmediate(N.getOperand(3),Tmp3) && (Tmp3 == 0);
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bool IM = isIntImmediate(N.getOperand(2),Tmp3) && ((signed)Tmp3 >= -32768 ||
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(signed)Tmp3 < 32768);
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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if (!IM || N.getOpcode() == ISD::SUB_PARTS)
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Tmp3 = SelectExpr(N.getOperand(2));
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if ((!ME && !ZE) || N.getOpcode() == ISD::SUB_PARTS)
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Tmp4 = SelectExpr(N.getOperand(3));
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if (N.getOpcode() == ISD::ADD_PARTS) {
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BuildMI(BB, PPC::ADDC, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
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BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
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// Codegen the low 32 bits of the add. Interestingly, there is no shifted
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// form of add immediate carrying.
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if (IM)
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BuildMI(BB, PPC::ADDIC, 2, Result).addReg(Tmp1).addSImm(Tmp3);
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else
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BuildMI(BB, PPC::ADDC, 2, Result).addReg(Tmp1).addReg(Tmp3);
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// Codegen the high 32 bits, adding zero, minus one, or the full value
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// along with the carry flag produced by addc/addic to tmp2.
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if (ZE)
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BuildMI(BB, PPC::ADDZE, 1, Result+1).addReg(Tmp2);
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else if (ME)
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BuildMI(BB, PPC::ADDME, 1, Result+1).addReg(Tmp2);
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else
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BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(Tmp2).addReg(Tmp4);
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} else {
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BuildMI(BB, PPC::SUBFC, 2, Result).addReg(InVals[2]).addReg(InVals[0]);
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BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(InVals[3]).addReg(InVals[1]);
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BuildMI(BB, PPC::SUBFC, 2, Result).addReg(Tmp3).addReg(Tmp1);
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BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(Tmp4).addReg(Tmp2);
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}
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return Result+N.ResNo;
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}
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@ -1716,10 +1736,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::Constant:
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switch (N.getValueType()) {
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default: assert(0 && "Cannot use constants of this type!");
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case MVT::i1:
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BuildMI(BB, PPC::LI, 1, Result)
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.addSImm(!cast<ConstantSDNode>(N)->isNullValue());
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break;
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case MVT::i32:
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{
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int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
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