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ARM rot_imm printing adjustment.

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Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-07-26 21:44:37 +00:00
parent 85bfd3b023
commit 45f3929ef0
3 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/ARM/ARMInstrInfo.td
View File

@@ -999,7 +999,7 @@ multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
let Inst{3-0} = Rm; let Inst{3-0} = Rm;
} }
def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot), def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$Rd, $Rm, $rot", IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
[(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>, [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
bits<4> Rd; bits<4> Rd;
@@ -1021,7 +1021,7 @@ multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
let Inst{11-10} = 0b00; let Inst{11-10} = 0b00;
} }
def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot), def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$Rd, $Rm, $rot", IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
bits<2> rot; bits<2> rot;
@@ -1048,7 +1048,7 @@ multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
} }
def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
rot_imm:$rot), rot_imm:$rot),
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, $rot", IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
[(set GPR:$Rd, (opnode GPR:$Rn, [(set GPR:$Rd, (opnode GPR:$Rn,
(rotr GPR:$Rm, rot_imm:$rot)))]>, (rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
@@ -1074,7 +1074,7 @@ multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
} }
def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
rot_imm:$rot), rot_imm:$rot),
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, $rot", IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
[/* For disassembly only; pattern left blank */]>, [/* For disassembly only; pattern left blank */]>,
Requires<[IsARM, HasV6]> { Requires<[IsARM, HasV6]> {
bits<4> Rn; bits<4> Rn;

8
lib/Target/ARM/ARMInstrThumb2.td
View File

@@ -990,7 +990,7 @@ multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
let Inst{5-4} = 0b00; // rotate let Inst{5-4} = 0b00; // rotate
} }
def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
opc, ".w\t$Rd, $Rm, $rot", opc, ".w\t$Rd, $Rm$rot",
[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> { [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
@@ -1019,7 +1019,7 @@ multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
let Inst{5-4} = 0b00; // rotate let Inst{5-4} = 0b00; // rotate
} }
def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot), def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
IIC_iEXTr, opc, "\t$dst, $Rm, $rot", IIC_iEXTr, opc, "\t$dst, $Rm$rot",
[(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack, IsThumb2]> { Requires<[HasT2ExtractPack, IsThumb2]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
@@ -1079,7 +1079,7 @@ multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
} }
def rr_rot : T2ThreeReg<(outs rGPR:$Rd), def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, $rot", IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
[(set rGPR:$Rd, (opnode rGPR:$Rn, [(set rGPR:$Rd, (opnode rGPR:$Rn,
(rotr rGPR:$Rm, rot_imm:$rot)))]>, (rotr rGPR:$Rm, rot_imm:$rot)))]>,
Requires<[HasT2ExtractPack, IsThumb2]> { Requires<[HasT2ExtractPack, IsThumb2]> {
@@ -1105,7 +1105,7 @@ multiclass T2I_exta_rrot_np<bits<3> opcod, string opc> {
let Inst{5-4} = 0b00; // rotate let Inst{5-4} = 0b00; // rotate
} }
def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, $rot", []> { IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod; let Inst{22-20} = opcod;

2
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@@ -841,7 +841,7 @@ void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
unsigned Imm = MI->getOperand(OpNum).getImm(); unsigned Imm = MI->getOperand(OpNum).getImm();
if (Imm == 0) if (Imm == 0)
return; return;
O << "ror #"; O << ", ror #";
switch (Imm) { switch (Imm) {
default: assert (0 && "illegal ror immediate!"); default: assert (0 && "illegal ror immediate!");
case 1: O << "8\n"; break; case 1: O << "8\n"; break;