Add titles to the various SelectionDAG viewGraph calls

that include useful information like the name of the
block being viewed and the current phase of compilation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53872 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-07-21 20:00:07 +00:00
parent 2d3ff5a7ae
commit 462dc7f496
8 changed files with 69 additions and 56 deletions

View File

@ -84,7 +84,8 @@ public:
/// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
///
void viewGraph();
void viewGraph(const std::string &Title);
void viewGraph() { return viewGraph(""); }
#ifndef NDEBUG
std::map<const SDNode *, std::string> NodeGraphAttrs;

View File

@ -59,7 +59,7 @@ public:
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
virtual void InstructionSelect(SelectionDAG &SD) = 0;
virtual void InstructionSelectPostProcessing(SelectionDAG &DAG) {}
virtual void InstructionSelectPostProcessing() {}
virtual void SelectRootInit() {
DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);

View File

@ -37,20 +37,6 @@ STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
namespace {
#ifndef NDEBUG
static cl::opt<bool>
ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before the first "
"dag combine pass"));
static cl::opt<bool>
ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before the second "
"dag combine pass"));
#else
static const bool ViewDAGCombine1 = false;
static const bool ViewDAGCombine2 = false;
#endif
static cl::opt<bool>
CombinerAA("combiner-alias-analysis", cl::Hidden,
cl::desc("Turn on alias analysis during testing"));
@ -5662,10 +5648,6 @@ SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
// SelectionDAG::Combine - This is the entry point for the file.
//
void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
if (!RunningAfterLegalize && ViewDAGCombine1)
viewGraph();
if (RunningAfterLegalize && ViewDAGCombine2)
viewGraph();
/// run - This is the main entry point to this class.
///
DAGCombiner(*this, AA).Run(RunningAfterLegalize);

View File

@ -35,14 +35,6 @@
#include <map>
using namespace llvm;
#ifndef NDEBUG
static cl::opt<bool>
ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before legalize"));
#else
static const bool ViewLegalizeDAGs = 0;
#endif
//===----------------------------------------------------------------------===//
/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
/// hacks on it until the target machine can handle it. This involves
@ -7039,8 +7031,6 @@ SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
// SelectionDAG::Legalize - This is the entry point for the file.
//
void SelectionDAG::Legalize() {
if (ViewLegalizeDAGs) viewGraph();
/// run - This is the main entry point to this class.
///
SelectionDAGLegalize(*this).LegalizeDAG();

View File

@ -19,15 +19,6 @@
#include "llvm/Target/TargetData.h"
using namespace llvm;
#ifndef NDEBUG
static cl::opt<bool>
ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before legalize types"));
#else
static const bool ViewLegalizeTypesDAGs = 0;
#endif
/// run - This is the main entry point for the type legalizer. This does a
/// top-down traversal of the dag, legalizing types as it goes.
void DAGTypeLegalizer::run() {
@ -673,7 +664,5 @@ void DAGTypeLegalizer::GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT) {
/// Note that this is an involved process that may invalidate pointers into
/// the graph.
void SelectionDAG::LegalizeTypes() {
if (ViewLegalizeTypesDAGs) viewGraph();
DAGTypeLegalizer(*this).run();
}

View File

@ -57,6 +57,20 @@ EnableLegalizeTypes("enable-legalize-types", cl::Hidden);
#ifndef NDEBUG
static cl::opt<bool>
ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before the first "
"dag combine pass"));
static cl::opt<bool>
ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before legalize types"));
static cl::opt<bool>
ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before legalize"));
static cl::opt<bool>
ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before the second "
"dag combine pass"));
static cl::opt<bool>
ViewISelDAGs("view-isel-dags", cl::Hidden,
cl::desc("Pop up a window to show isel dags as they are selected"));
static cl::opt<bool>
@ -66,7 +80,11 @@ static cl::opt<bool>
ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
cl::desc("Pop up a window to show SUnit dags after they are processed"));
#else
static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0, ViewSUnitDAGs = 0;
static const bool ViewDAGCombine1 = false,
ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
ViewDAGCombine2 = false,
ViewISelDAGs = false, ViewSchedDAGs = false,
ViewSUnitDAGs = false;
#endif
//===---------------------------------------------------------------------===//
@ -5282,9 +5300,19 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
}
void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
DOUT << "Lowered selection DAG:\n";
std::string GroupName;
if (TimePassesIsEnabled)
GroupName = "Instruction Selection and Scheduling";
std::string BlockName;
if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
BB->getBasicBlock()->getName();
DOUT << "Initial selection DAG:\n";
DEBUG(DAG.dump());
std::string GroupName = "Instruction Selection and Scheduling";
if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
// Run the DAG combiner in pre-legalize mode.
if (TimePassesIsEnabled) {
@ -5300,10 +5328,24 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
// Second step, hack on the DAG until it only uses operations and types that
// the target supports.
if (EnableLegalizeTypes) {// Enable this some day.
DAG.LegalizeTypes();
if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
BlockName);
if (TimePassesIsEnabled) {
NamedRegionTimer T("Type Legalization", GroupName);
DAG.LegalizeTypes();
} else {
DAG.LegalizeTypes();
}
DOUT << "Type-legalized selection DAG:\n";
DEBUG(DAG.dump());
// TODO: enable a dag combine pass here.
}
if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
if (TimePassesIsEnabled) {
NamedRegionTimer T("DAG Legalization", GroupName);
DAG.Legalize();
@ -5314,6 +5356,8 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
DOUT << "Legalized selection DAG:\n";
DEBUG(DAG.dump());
if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
// Run the DAG combiner in post-legalize mode.
if (TimePassesIsEnabled) {
NamedRegionTimer T("DAG Combining 2", GroupName);
@ -5325,7 +5369,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
DOUT << "Optimized legalized selection DAG:\n";
DEBUG(DAG.dump());
if (ViewISelDAGs) DAG.viewGraph();
if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
if (!FastISel && EnableValueProp)
ComputeLiveOutVRegInfo(DAG);
@ -5339,6 +5383,11 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
InstructionSelect(DAG);
}
DOUT << "Selected selection DAG:\n";
DEBUG(DAG.dump());
if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
// Schedule machine code.
ScheduleDAG *Scheduler;
if (TimePassesIsEnabled) {
@ -5348,6 +5397,8 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
Scheduler = Schedule(DAG);
}
if (ViewSUnitDAGs) Scheduler->viewGraph();
// Emit machine code to BB. This can change 'BB' to the last block being
// inserted into.
if (TimePassesIsEnabled) {
@ -5368,9 +5419,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
// Perform target specific isel post processing.
if (TimePassesIsEnabled) {
NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
InstructionSelectPostProcessing(DAG);
InstructionSelectPostProcessing();
} else {
InstructionSelectPostProcessing(DAG);
InstructionSelectPostProcessing();
}
DOUT << "Selected machine code:\n";
@ -5619,8 +5670,6 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
/// target node in the graph.
///
ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
if (ViewSchedDAGs) DAG.viewGraph();
RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
if (!Ctor) {
@ -5631,7 +5680,6 @@ ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel);
Scheduler->Run();
if (ViewSUnitDAGs) Scheduler->viewGraph();
return Scheduler;
}

View File

@ -215,10 +215,11 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG
/// rendered using 'dot'.
///
void SelectionDAG::viewGraph() {
void SelectionDAG::viewGraph(const std::string &Title) {
// This code is only for debugging!
#ifndef NDEBUG
ViewGraph(this, "dag." + getMachineFunction().getFunction()->getName());
ViewGraph(this, "dag." + getMachineFunction().getFunction()->getName(),
Title);
#else
cerr << "SelectionDAG::viewGraph is only available in debug builds on "
<< "systems with Graphviz or gv!\n";
@ -348,7 +349,9 @@ std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
void ScheduleDAG::viewGraph() {
// This code is only for debugging!
#ifndef NDEBUG
ViewGraph(this, "dag." + DAG.getMachineFunction().getFunction()->getName());
ViewGraph(this, "dag." + MF->getFunction()->getName(),
"Scheduling-Units Graph for " + MF->getFunction()->getName() + ':' +
BB->getBasicBlock()->getName());
#else
cerr << "ScheduleDAG::viewGraph is only available in debug builds on "
<< "systems with Graphviz or gv!\n";

View File

@ -133,7 +133,7 @@ namespace {
/// InstructionSelectPostProcessing - Post processing of selected and
/// scheduled basic blocks.
virtual void InstructionSelectPostProcessing(SelectionDAG &DAG);
virtual void InstructionSelectPostProcessing();
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
@ -580,7 +580,7 @@ void X86DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
DAG.RemoveDeadNodes();
}
void X86DAGToDAGISel::InstructionSelectPostProcessing(SelectionDAG &DAG) {
void X86DAGToDAGISel::InstructionSelectPostProcessing() {
// If we are emitting FP stack code, scan the basic block to determine if this
// block defines any FP values. If so, put an FP_REG_KILL instruction before
// the terminator of the block.