6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-06 06:33:24 +00:00
Code Issues Projects Releases Wiki Activity

The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.

Browse Source 
rdar://problem/9279440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-13 21:04:32 +00:00
parent 5af60ce2a8
commit 471d73d5d3
3 changed files with 26 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1381,7 +1381,7 @@ def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
// for disassembly only. // for disassembly only.
// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
: T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
"\t$Rt, $addr", []> { "\t$Rt, $addr", []> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;
@ -1472,7 +1472,7 @@ def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
// only. // only.
// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
class T2IstT<bits<2> type, string opc, InstrItinClass ii> class T2IstT<bits<2> type, string opc, InstrItinClass ii>
: T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
"\t$Rt, $addr", []> { "\t$Rt, $addr", []> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-25} = 0b00; let Inst{26-25} = 0b00;

20
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -1909,6 +1909,8 @@ static bool BadRegsThumb2LdSt(unsigned Opcode, uint32_t insn, bool Load,
// Inst{22-21} encodes the data item transferred for load/store. // Inst{22-21} encodes the data item transferred for load/store.
// For single word, it is encoded as ob10. // For single word, it is encoded as ob10.
bool Word = (slice(insn, 22, 21) == 2); bool Word = (slice(insn, 22, 21) == 2);
bool Half = (slice(insn, 22, 21) == 1);
bool Byte = (slice(insn, 22, 21) == 0);
if (UseRm && BadReg(R2)) { if (UseRm && BadReg(R2)) {
DEBUG(errs() << "if BadReg(m) then UNPREDICTABLE\n"); DEBUG(errs() << "if BadReg(m) then UNPREDICTABLE\n");
@ -1920,9 +1922,15 @@ static bool BadRegsThumb2LdSt(unsigned Opcode, uint32_t insn, bool Load,
DEBUG(errs() << "if t == 13 then UNPREDICTABLE\n"); DEBUG(errs() << "if t == 13 then UNPREDICTABLE\n");
return true; return true;
} }
if (Byte) {
if (WB && R0 == 15 && slice(insn, 10, 8) == 3) {
// A8.6.78 LDRSB (immediate) Encoding T2 (errata markup 8.0)
DEBUG(errs() << "if t == 15 && PUW == '011' then UNPREDICTABLE\n");
return true;
}
}
// A6.3.8 Load halfword, memory hints // A6.3.8 Load halfword, memory hints
const StringRef Name = ARMInsts[Opcode].Name; if (Half) {
if (Name.startswith("t2LDRH") || Name.startswith("t2LDRSH")) {
if (WB) { if (WB) {
if (R0 == R1) { if (R0 == R1) {
// A8.6.82 LDRSH (immediate) Encoding T2 // A8.6.82 LDRSH (immediate) Encoding T2
@ -2021,8 +2029,8 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
OpIdx = 0; OpIdx = 0;
assert(NumOps >= 3 && assert(NumOps >= 3 &&
OpInfo[0].RegClass == ARM::GPRRegClassID && OpInfo[0].RegClass > 0 &&
OpInfo[1].RegClass == ARM::GPRRegClassID && OpInfo[1].RegClass > 0 &&
"Expect >= 3 operands and first two as reg operands"); "Expect >= 3 operands and first two as reg operands");
bool ThreeReg = (OpInfo[2].RegClass > 0); bool ThreeReg = (OpInfo[2].RegClass > 0);
@ -2061,10 +2069,10 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
Imm = decodeImm8(insn); Imm = decodeImm8(insn);
} }
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
R0))); R0)));
++OpIdx; ++OpIdx;
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
R1))); R1)));
++OpIdx; ++OpIdx;

10
test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt Normal file
View File

@ -0,0 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# The unpriviledged Load/Store cannot have SP or PC as Rt.
0x10 0xf8 0x3 0xfe