6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-19 04:32:19 +00:00
Code Issues Projects Releases Wiki Activity

Fix PromoteIntRes_TRUNCATE: Add support for cases where the

Browse Source 
source vector type is to be split while the target vector is to be promoted.
(eg: <4 x i64> -> <4 x i8> )


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133424 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2011-06-20 07:15:58 +00:00
parent 289a27946f
commit 4720611025
2 changed files with 39 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -520,20 +520,44 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDValue Res;
SDValue InOp = N->getOperand(0);
DebugLoc dl = N->getDebugLoc();
switch (getTypeAction(N->getOperand(0).getValueType())) {
switch (getTypeAction(InOp.getValueType())) {
default: llvm_unreachable("Unknown type action!");
case TargetLowering::TypeLegal:
case TargetLowering::TypeExpandInteger:
Res = N->getOperand(0);
Res = InOp;
break;
case TargetLowering::TypePromoteInteger:
Res = GetPromotedInteger(N->getOperand(0));
Res = GetPromotedInteger(InOp);
break;
case TargetLowering::TypeSplitVector:
EVT InVT = InOp.getValueType();
assert(InVT.isVector() && "Cannot split scalar types");
unsigned NumElts = InVT.getVectorNumElements();
assert(NumElts == NVT.getVectorNumElements() &&
"Dst and Src must have the same number of elements");
EVT EltVT = InVT.getScalarType();
assert(isPowerOf2_32(NumElts) &&
"Promoted vector type must be a power of two");
EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts/2);
EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
NumElts/2);
SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
DAG.getIntPtrConstant(0));
SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
DAG.getIntPtrConstant(NumElts/2));
EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
}
// Truncate to NVT instead of VT
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
}
SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {

11
test/CodeGen/X86/promote-trunc.ll Normal file
View File

@ -0,0 +1,11 @@
; RUN: llc -promote-elements < %s -march=x86-64
define<4 x i8> @func_8_64() {
%F = load <4 x i64>* undef
%G = trunc <4 x i64> %F to <4 x i8>
%H = load <4 x i64>* undef
%Y = trunc <4 x i64> %H to <4 x i8>
%T = add <4 x i8> %Y, %G
ret <4 x i8> %T
}