6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-01 01:30:36 +00:00
Code Issues Projects Releases Wiki Activity

Eliminate spurious empty space; make code easier to page through.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15146 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-07-23 22:35:49 +00:00
parent 1245c35935
commit 4722544855
2 changed files with 24 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -441,8 +441,7 @@ unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
/// is okay to use as an immediate argument to a certain binary operator.
///
/// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator)
{
bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
ConstantSInt *Op1Cs;
ConstantUInt *Op1Cu;
@ -795,7 +794,6 @@ void ISel::SelectPHINodes() {
// We already inserted an initialization of the register for this
// predecessor. Recycle it.
ValReg = EntryIt->second;
} else {
// Get the incoming value into a virtual register.
//
@ -1108,14 +1106,11 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
// to get the register of the Cond value
if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
// We successfully folded the setcc into the select instruction.
unsigned OpNum = getSetCCNumber(SCI->getOpcode());
OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
IP);
OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
} else {
unsigned CondReg = getReg(Cond, MBB, IP);
BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(CondReg).addSImm(0);
Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
}
@ -1209,7 +1204,6 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
// Make sure we have the register number for this value...
unsigned Reg = Val ? getReg(Val) : VR.Reg;
switch (getClassB(Ty)) {
case cByte:
// Extend value into target register (8->32)
@ -2886,11 +2880,8 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
}
}
// Do some statistical accounting
if (ops.empty())
++GEPConsts;
if (anyCombined)
++GEPSplits;
if (ops.empty()) ++GEPConsts;
if (anyCombined) ++GEPSplits;
// Emit instructions for all the collapsed ops
for(std::vector<CollapsedGepOp *>::iterator cgo_i = ops.begin(),

17
lib/Target/PowerPC/PowerPCISelSimple.cpp
View File

@ -441,8 +441,7 @@ unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
/// is okay to use as an immediate argument to a certain binary operator.
///
/// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator)
{
bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
ConstantSInt *Op1Cs;
ConstantUInt *Op1Cu;
@ -795,7 +794,6 @@ void ISel::SelectPHINodes() {
// We already inserted an initialization of the register for this
// predecessor. Recycle it.
ValReg = EntryIt->second;
} else {
// Get the incoming value into a virtual register.
//
@ -1108,14 +1106,11 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
// to get the register of the Cond value
if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
// We successfully folded the setcc into the select instruction.
unsigned OpNum = getSetCCNumber(SCI->getOpcode());
OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
IP);
OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
} else {
unsigned CondReg = getReg(Cond, MBB, IP);
BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(CondReg).addSImm(0);
Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
}
@ -1209,7 +1204,6 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
// Make sure we have the register number for this value...
unsigned Reg = Val ? getReg(Val) : VR.Reg;
switch (getClassB(Ty)) {
case cByte:
// Extend value into target register (8->32)
@ -2886,11 +2880,8 @@ void ISel::emitGEPOperation(MachineBasicBlock *MBB,
}
}
// Do some statistical accounting
if (ops.empty())
++GEPConsts;
if (anyCombined)
++GEPSplits;
if (ops.empty()) ++GEPConsts;
if (anyCombined) ++GEPSplits;
// Emit instructions for all the collapsed ops
for(std::vector<CollapsedGepOp *>::iterator cgo_i = ops.begin(),