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Added documentation for SizeMultiplier in the ARM subtarget hook for register coalescing. Also fixed some 80 col violations.
No functional code changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213169 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -476,8 +476,17 @@ bool ARMSubtarget::shouldCoalesce(MachineInstr *MI,
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auto AFI = MF->getInfo<ARMFunctionInfo>();
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auto It = AFI->getCoalescedWeight(MBB);
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DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " << It->second << "\n");
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DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " << NewRCWeight.RegWeight << "\n");
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DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
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<< It->second << "\n");
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DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
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<< NewRCWeight.RegWeight << "\n");
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// This number is the largest round number that which meets the criteria:
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// (1) addresses PR18825
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// (2) generates better code in some test cases (like vldm-shed-a9.ll)
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// (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
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// In practice the SizeMultiplier will only factor in for straight line code
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// that uses a lot of NEON vectors, which isn't terribly common.
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unsigned SizeMultiplier = MBB->size()/100;
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SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
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if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
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