Merging r229230:

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r229230 | Matthew.Arsenault | 2015-02-13 22:40:35 -0500 (Fri, 13 Feb 2015) | 4 lines

R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}

This apparently got lost in the VI changes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235678 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/R600/SIInstrInfo.td

@@ -1015,6 +1015,19 @@ multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
   } // End sdst = SIOperand.VCC, Defs = [VCC]
 }
 
+multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
+                      list<dag> pattern, string opName, string revOp,
+                      bit HasMods = 1, bit UseFullOp = 0> {
+  def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
+
+
+  def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
+            VOP3DisableFields<1, 1, HasMods>;
+
+  def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
+            VOP3DisableFields<1, 1, HasMods>;
+}
+
 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
                      list<dag> pattern, string opName,
                      bit HasMods, bit defExec> {
@@ -1316,7 +1329,7 @@ multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
 
 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
                     string opName, list<dag> pattern> :
-  VOP3b_2_m <
+  VOP3b_3_m <
   op, (outs vrc:$vdst, SReg_64:$sdst),
       (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
            InputModsNoDefault:$src1_modifiers, arc:$src1,