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Fixed register allocator splitting a live range on a spilling variable.
If we create new intervals for a variable that is being spilled, then those new intervals are not guaranteed to also spill. This means that anything reading from the original spilling value might not get the correct value if spills were missed. Fixes <rdar://problem/10546864> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146428 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -957,7 +957,7 @@ void InlineSpiller::reMaterializeAll() {
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if (DeadDefs.empty())
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return;
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DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
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Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII);
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Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII, RegsToSpill);
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// Get rid of deleted and empty intervals.
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for (unsigned i = RegsToSpill.size(); i != 0; --i) {
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@ -1240,7 +1240,7 @@ void InlineSpiller::spillAll() {
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// Hoisted spills may cause dead code.
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if (!DeadDefs.empty()) {
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DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
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Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII);
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Edit->eliminateDeadDefs(DeadDefs, LIS, VRM, TII, RegsToSpill);
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}
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// Finally delete the SnippetCopies.
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@ -210,7 +210,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
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void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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LiveIntervals &LIS, VirtRegMap &VRM,
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const TargetInstrInfo &TII) {
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const TargetInstrInfo &TII,
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ArrayRef<unsigned> RegsBeingSpilled) {
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SetVector<LiveInterval*,
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SmallVector<LiveInterval*, 8>,
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SmallPtrSet<LiveInterval*, 8> > ToShrink;
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@ -290,6 +291,21 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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delegate_->LRE_WillShrinkVirtReg(LI->reg);
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if (!LIS.shrinkToUses(LI, &Dead))
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continue;
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// Don't create new intervals for a register being spilled.
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// The new intervals would have to be spilled anyway so its not worth it.
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// Also they currently aren't spilled so creating them and not spilling
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// them results in incorrect code.
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bool BeingSpilled = false;
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for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
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if (LI->reg == RegsBeingSpilled[i]) {
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BeingSpilled = true;
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break;
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}
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}
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if (BeingSpilled) continue;
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// LI may have been separated, create new intervals.
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LI->RenumberValues(LIS);
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@ -191,9 +191,14 @@ public:
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/// eliminateDeadDefs - Try to delete machine instructions that are now dead
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/// (allDefsAreDead returns true). This may cause live intervals to be trimmed
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/// and further dead efs to be eliminated.
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/// RegsBeingSpilled lists registers currently being spilled by the register
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/// allocator. These registers should not be split into new intervals
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/// as currently those new intervals are not guaranteed to spill.
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void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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LiveIntervals&, VirtRegMap&,
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const TargetInstrInfo&);
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const TargetInstrInfo&,
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ArrayRef<unsigned> RegsBeingSpilled
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= ArrayRef<unsigned>());
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/// calculateRegClassAndHint - Recompute register class and hint for each new
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/// register.
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