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There is no need to call MachineInstr::print directly, just send the MI& to an ostream.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16613 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-09-30 16:10:45 +00:00
parent 70ca358b7d
commit 477e4555de
2 changed files with 18 additions and 18 deletions
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19
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -180,8 +180,7 @@ void LiveIntervals::print(std::ostream &O) const {
O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n";
for (MachineBasicBlock::iterator mii = mbbi->begin(),
mie = mbbi->end(); mii != mie; ++mii) {
O << getInstructionIndex(mii) << '\t';
mii->print(O, tm_);
O << getInstructionIndex(mii) << '\t' << *mii;
}
}
}
@ -219,6 +218,9 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
for (unsigned i = 0; i != mi->getNumOperands(); ++i) {
MachineOperand& mop = mi->getOperand(i);
if (mop.isRegister() && mop.getReg() == li.reg) {
// First thing, attempt to fold the memory reference into the
// instruction. If we can do this, we don't need to insert spill
// code.
if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) {
if (lv_)
lv_->instructionChanged(mi, fmi);
@ -226,12 +228,14 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
mi2iMap_.erase(mi);
i2miMap_[index/InstrSlots::NUM] = fmi;
mi2iMap_[fmi] = index;
MachineBasicBlock& mbb = *mi->getParent();
mi = mbb.insert(mbb.erase(mi), fmi);
MachineBasicBlock &MBB = *mi->getParent();
mi = MBB.insert(MBB.erase(mi), fmi);
++numFolded;
// Folding the load/store can completely change the instruction in
// unpredictable ways, rescan it from the beginning.
goto for_operand;
}
else {
} else {
// This is tricky. We need to add information in the interval about
// the spill code so we have to use our extra load/store slots.
//
@ -519,8 +523,7 @@ void LiveIntervals::computeIntervals()
mi != miEnd; ++mi) {
const TargetInstrDescriptor& tid =
tm_->getInstrInfo()->get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
mi->print(std::cerr, tm_));
DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi);
// handle implicit defs
for (const unsigned* id = tid.ImplicitDefs; *id; ++id)

17
lib/CodeGen/VirtRegMap.cpp
View File

@ -153,7 +153,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
unsigned VirtReg = MOP.getReg();
unsigned PhysReg = VRM.getPhys(VirtReg);
if (VRM.hasStackSlot(VirtReg)) {
int StackSlot = VRM.getStackSlot(VirtReg);
int StackSlot = VRM.getStackSlot(VirtReg);
if (MOP.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
@ -161,7 +161,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
LoadedRegs.push_back(VirtReg);
++NumLoads;
DEBUG(std::cerr << '\t'; prior(MII)->print(std::cerr, &TM));
DEBUG(std::cerr << '\t' << *prior(MII));
}
if (MOP.isDef()) {
@ -173,7 +173,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
MI.SetMachineOperandReg(i, PhysReg);
}
}
DEBUG(std::cerr << '\t'; MI.print(std::cerr, &TM));
DEBUG(std::cerr << '\t' << MI);
LoadedRegs.clear();
}
}
@ -228,8 +228,7 @@ namespace {
MRI->loadRegFromStackSlot(MBB, MII, PhysReg,
VRM->getStackSlot(VirtReg));
++NumLoads;
DEBUG(std::cerr << "added: ";
prior(MII)->print(std::cerr, TM));
DEBUG(std::cerr << "added: " << *prior(MII));
lastDef_[VirtReg] = MII;
}
}
@ -293,10 +292,8 @@ void LocalSpiller::vacateJustPhysReg(MachineBasicBlock& MBB,
PhysReg,
VRM->getStackSlot(VirtReg));
++NumStores;
DEBUG(std::cerr << "added: ";
prior(nextLastRef)->print(std::cerr, TM);
std::cerr << "after: ";
lastDef->print(std::cerr, TM));
DEBUG(std::cerr << "added: " << *prior(nextLastRef);
std::cerr << "after: " << *lastDef);
lastDef_[VirtReg] = 0;
}
p2vMap_[PhysReg] = 0;
@ -360,7 +357,7 @@ void LocalSpiller::eliminateVirtRegsInMBB(MachineBasicBlock &MBB) {
}
}
DEBUG(std::cerr << '\t'; MI->print(std::cerr, TM));
DEBUG(std::cerr << '\t' << *MI);
}
for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)