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Use getAL() rather than a major constant.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101446 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-04-16 05:46:06 +00:00
parent 0772751edd
commit 47b7b9f228
1 changed files with 9 additions and 9 deletions
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18
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@@ -996,7 +996,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
break; break;
} }
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (is64BitVector) { if (is64BitVector) {
unsigned Opc = DOpcodes[OpcodeIndex]; unsigned Opc = DOpcodes[OpcodeIndex];
@@ -1086,7 +1086,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
break; break;
} }
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SmallVector<SDValue, 10> Ops; SmallVector<SDValue, 10> Ops;
@@ -1193,7 +1193,7 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
case MVT::v4i32: OpcodeIndex = 1; break; case MVT::v4i32: OpcodeIndex = 1; break;
} }
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SmallVector<SDValue, 10> Ops; SmallVector<SDValue, 10> Ops;
@@ -1475,7 +1475,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
SDNode *ResNode; SDNode *ResNode;
if (Subtarget->isThumb1Only()) { if (Subtarget->isThumb1Only()) {
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
@@ -1650,7 +1650,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
SDValue Chain = N->getOperand(0); SDValue Chain = N->getOperand(0);
SDValue AM5Opc = SDValue AM5Opc =
CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32); CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain }; SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain };
return CurDAG->getMachineNode(ARM::VLDMQ, dl, MVT::v2f64, MVT::Other, return CurDAG->getMachineNode(ARM::VLDMQ, dl, MVT::v2f64, MVT::Other,
@@ -1666,7 +1666,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
SDValue Chain = N->getOperand(0); SDValue Chain = N->getOperand(0);
SDValue AM5Opc = SDValue AM5Opc =
CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32); CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(1), N->getOperand(2), SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
AM5Opc, Pred, PredReg, Chain }; AM5Opc, Pred, PredReg, Chain };
@@ -1758,7 +1758,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case MVT::v4f32: case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VZIPq32; break; case MVT::v4i32: Opc = ARM::VZIPq32; break;
} }
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
@@ -1777,7 +1777,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case MVT::v4f32: case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VUZPq32; break; case MVT::v4i32: Opc = ARM::VUZPq32; break;
} }
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
@@ -1796,7 +1796,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
case MVT::v4f32: case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VTRNq32; break; case MVT::v4i32: Opc = ARM::VTRNq32; break;
} }
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32); SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4); return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);