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Implement cleanups suggested by Daniel.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121875 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2010-12-15 18:48:27 +00:00
parent 49e41c5179
commit 47dbd429da
3 changed files with 17 additions and 13 deletions
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4
include/llvm/MC/MCCodeEmitter.h
View File

@ -27,8 +27,8 @@ struct MCFixupKindInfo {
/// evaluate fixup values in a target independent manner when possible.
FKF_IsPCRel = (1 << 0),
// Should this fixup kind force a 4-byte aligned effective PC value?
FKF_IsAligned = (1 << 1)
/// Should this fixup kind force a 4-byte aligned effective PC value?
FKF_IsAlignedDownTo32Bits = (1 << 1)
};
/// A target specific name for the fixup kind. The names will be unique for

18
lib/MC/MCAssembler.cpp
View File

@ -248,14 +248,18 @@ bool MCAssembler::EvaluateFixup(const MCObjectWriter &Writer,
if (IsResolved)
IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF);
bool ShouldAlignPC = Emitter.getFixupKindInfo(Fixup.getKind()).Flags &
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits;
assert((ShouldAlignPC ? IsPCRel : true) &&
"FKF_IsAlignedDownTo32Bits is only allowed on PC-relative fixups!");
if (IsPCRel) {
bool ShouldAlignPC = Emitter.getFixupKindInfo(
Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsAligned;
// PC should be aligned to a 4-byte value.
if (ShouldAlignPC)
Value -= Layout.getFragmentOffset(DF) + (Fixup.getOffset() & ~0x3);
else
Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
uint32_t Offset = Fixup.getOffset();
// A number of ARM fixups in Thumb mode require that the effective PC
// address be determined as the 32-bit aligned version of the actual offset.
if (ShouldAlignPC) Offset &= 0x3;
Value -= Layout.getFragmentOffset(DF) + Offset;
}
// ARM fixups based from a thumb function address need to have the low

8
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -51,15 +51,15 @@ public:
// Name Offset (bits) Size (bits) Flags
{ "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAligned},
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAligned},
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAligned},
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAligned},
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{ "fixup_arm_branch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },