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Initial implementation of 'fence' instruction, the new C++0x-style replacement for llvm.memory.barrier.
This is just a LangRef entry and reading/writing/memory representation; optimizer+codegen support coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136009 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -1098,6 +1098,7 @@ public:
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void writeOperand(const Value *Op, bool PrintType);
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void writeParamOperand(const Value *Operand, Attributes Attrs);
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void writeAtomic(AtomicOrdering Ordering, SynchronizationScope SynchScope);
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void writeAllMDNodes();
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@@ -1128,6 +1129,28 @@ void AssemblyWriter::writeOperand(const Value *Operand, bool PrintType) {
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WriteAsOperandInternal(Out, Operand, &TypePrinter, &Machine, TheModule);
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}
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void AssemblyWriter::writeAtomic(AtomicOrdering Ordering,
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SynchronizationScope SynchScope) {
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if (Ordering == NotAtomic)
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return;
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switch (SynchScope) {
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default: Out << " <bad scope " << int(SynchScope) << ">"; break;
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case SingleThread: Out << " singlethread"; break;
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case CrossThread: break;
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}
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switch (Ordering) {
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default: Out << " <bad ordering " << int(Ordering) << ">"; break;
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case Unordered: Out << " unordered"; break;
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case Monotonic: Out << " monotonic"; break;
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case Acquire: Out << " acquire"; break;
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case Release: Out << " release"; break;
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case AcquireRelease: Out << " acq_rel"; break;
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case SequentiallyConsistent: Out << " seq_cst"; break;
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}
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}
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void AssemblyWriter::writeParamOperand(const Value *Operand,
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Attributes Attrs) {
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if (Operand == 0) {
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@@ -1883,6 +1906,8 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
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Out << ", align " << cast<LoadInst>(I).getAlignment();
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} else if (isa<StoreInst>(I) && cast<StoreInst>(I).getAlignment()) {
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Out << ", align " << cast<StoreInst>(I).getAlignment();
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} else if (const FenceInst *FI = dyn_cast<FenceInst>(&I)) {
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writeAtomic(FI->getOrdering(), FI->getSynchScope());
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}
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// Print Metadata info.
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