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Flip -disable-post-RA-scheduler to -post-RA-scheduler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82803 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-09-25 21:38:11 +00:00
parent b7a8d400be
commit 483011018e
6 changed files with 13 additions and 11 deletions
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12
lib/CodeGen/LLVMTargetMachine.cpp
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@ -45,11 +45,13 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
// When this works it will be on by default.
// This is not enabled by default due to 1) high compile time cost, 2) it's not
// beneficial to all targets. The plan is to let targets decide whether this
// is enabled.
static cl::opt<bool>
DisablePostRAScheduler("disable-post-RA-scheduler",
cl::desc("Disable scheduling after register allocation"),
cl::init(true));
EnablePostRAScheduler("post-RA-scheduler",
cl::desc("Enable scheduling after register allocation"),
cl::init(false));
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
@ -324,7 +326,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM);
// Second pass scheduler.
if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) {
PM.add(createPostRAScheduler());
printAndVerify(PM);
}

2
test/CodeGen/ARM/2009-08-21-PostRAKill.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -post-RA-scheduler -avoid-hazards
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"

2
test/CodeGen/ARM/2009-08-21-PostRAKill2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"

2
test/CodeGen/ARM/2009-08-21-PostRAKill3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"

2
test/CodeGen/ARM/2009-08-21-PostRAKill4.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler=0 -avoid-hazards
; ModuleID = '<stdin>'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"

4
test/CodeGen/X86/break-anti-dependencies.ll
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@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86-64 -disable-post-RA-scheduler=false -break-anti-dependencies=false > %t
; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=false > %t
; RUN: grep {%xmm0} %t | count 14
; RUN: not grep {%xmm1} %t
; RUN: llc < %s -march=x86-64 -disable-post-RA-scheduler=false -break-anti-dependencies > %t
; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies > %t
; RUN: grep {%xmm0} %t | count 7
; RUN: grep {%xmm1} %t | count 7