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Flip -disable-post-RA-scheduler to -post-RA-scheduler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82803 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-09-25 21:38:11 +00:00
parent b7a8d400be
commit 483011018e
6 changed files with 13 additions and 11 deletions
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12
lib/CodeGen/LLVMTargetMachine.cpp
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@@ -45,11 +45,13 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
// When this works it will be on by default.
// This is not enabled by default due to 1) high compile time cost, 2) it's not
// beneficial to all targets. The plan is to let targets decide whether this
// is enabled.
static cl::opt<bool>
DisablePostRAScheduler("disable-post-RA-scheduler",
cl::desc("Disable scheduling after register allocation"),
cl::init(true));
EnablePostRAScheduler("post-RA-scheduler",
cl::desc("Enable scheduling after register allocation"),
cl::init(false));
// Enable or disable FastISel. Both options are needed, because
// FastISel is enabled by default with -fast, and we wish to be
@@ -324,7 +326,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
printAndVerify(PM);
// Second pass scheduler.
if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) {
PM.add(createPostRAScheduler());
printAndVerify(PM);
}