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TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
parent
17785fd392
commit
48605c3406
@ -16,41 +16,299 @@
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#include "CodeGenSchedule.h"
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#include "CodeGenTarget.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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// CodeGenModels ctor interprets machine model records and populates maps.
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#ifndef NDEBUG
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static void dumpIdxVec(const IdxVec &V) {
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for (unsigned i = 0, e = V.size(); i < e; ++i) {
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dbgs() << V[i] << ", ";
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}
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}
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#endif
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/// CodeGenModels ctor interprets machine model records and populates maps.
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CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
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const CodeGenTarget &TGT):
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Records(RK), Target(TGT), NumItineraryClasses(0), HasProcItineraries(false) {
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Records(RK), Target(TGT), NumItineraryClasses(0) {
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// Populate SchedClassIdxMap and set NumItineraryClasses.
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CollectSchedClasses();
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// Instantiate a CodeGenProcModel for each SchedMachineModel with the values
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// that are explicitly referenced in tablegen records. Resources associated
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// with each processor will be derived later. Populate ProcModelMap with the
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// CodeGenProcModel instances.
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collectProcModels();
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// Populate ProcModelMap.
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CollectProcModels();
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// Instantiate a CodeGenSchedRW for each SchedReadWrite record explicitly
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// defined, and populate SchedReads and SchedWrites vectors. Implicit
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// SchedReadWrites that represent sequences derived from expanded variant will
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// be inferred later.
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collectSchedRW();
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// Instantiate a CodeGenSchedClass for each unique SchedRW signature directly
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// required by an instruction definition, and populate SchedClassIdxMap. Set
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// NumItineraryClasses to the number of explicit itinerary classes referenced
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// by instructions. Set NumInstrSchedClasses to the number of itinerary
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// classes plus any classes implied by instructions that derive from class
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// Sched and provide SchedRW list. This does not infer any new classes from
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// SchedVariant.
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collectSchedClasses();
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// Find instruction itineraries for each processor. Sort and populate
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// CodeGenProcMode::ItinDefList. (Cycle-to-cycle itineraries). This requires
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// all itinerary classes to be discovered.
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collectProcItins();
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// Find ItinRW records for each processor and itinerary class.
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// (For per-operand resources mapped to itinerary classes).
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collectProcItinRW();
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}
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// Visit all the instruction definitions for this target to gather and enumerate
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// the itinerary classes. These are the explicitly specified SchedClasses. More
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// SchedClasses may be inferred.
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void CodeGenSchedModels::CollectSchedClasses() {
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/// Gather all processor models.
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void CodeGenSchedModels::collectProcModels() {
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RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");
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std::sort(ProcRecords.begin(), ProcRecords.end(), LessRecordFieldName());
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// NoItinerary is always the first class at Index=0
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// Reserve space because we can. Reallocation would be ok.
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ProcModels.reserve(ProcRecords.size()+1);
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// Use idx=0 for NoModel/NoItineraries.
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Record *NoModelDef = Records.getDef("NoSchedModel");
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Record *NoItinsDef = Records.getDef("NoItineraries");
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ProcModels.push_back(CodeGenProcModel(0, "NoSchedModel",
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NoModelDef, NoItinsDef));
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ProcModelMap[NoModelDef] = 0;
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// For each processor, find a unique machine model.
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for (unsigned i = 0, N = ProcRecords.size(); i < N; ++i)
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addProcModel(ProcRecords[i]);
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}
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/// Get a unique processor model based on the defined MachineModel and
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/// ProcessorItineraries.
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void CodeGenSchedModels::addProcModel(Record *ProcDef) {
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Record *ModelKey = getModelOrItinDef(ProcDef);
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if (!ProcModelMap.insert(std::make_pair(ModelKey, ProcModels.size())).second)
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return;
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std::string Name = ModelKey->getName();
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if (ModelKey->isSubClassOf("SchedMachineModel")) {
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Record *ItinsDef = ModelKey->getValueAsDef("Itineraries");
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ProcModels.push_back(
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CodeGenProcModel(ProcModels.size(), Name, ModelKey, ItinsDef));
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}
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else {
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// An itinerary is defined without a machine model. Infer a new model.
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if (!ModelKey->getValueAsListOfDefs("IID").empty())
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Name = Name + "Model";
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ProcModels.push_back(
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CodeGenProcModel(ProcModels.size(), Name,
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ProcDef->getValueAsDef("SchedModel"), ModelKey));
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}
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DEBUG(ProcModels.back().dump());
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}
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// Recursively find all reachable SchedReadWrite records.
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static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
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SmallPtrSet<Record*, 16> &RWSet) {
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if (!RWSet.insert(RWDef))
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return;
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RWDefs.push_back(RWDef);
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// Reads don't current have sequence records, but it can be added later.
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if (RWDef->isSubClassOf("WriteSequence")) {
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RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
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for (RecIter I = Seq.begin(), E = Seq.end(); I != E; ++I)
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scanSchedRW(*I, RWDefs, RWSet);
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}
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else if (RWDef->isSubClassOf("SchedVariant")) {
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// Visit each variant (guarded by a different predicate).
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RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
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for (RecIter VI = Vars.begin(), VE = Vars.end(); VI != VE; ++VI) {
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// Visit each RW in the sequence selected by the current variant.
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RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");
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for (RecIter I = Selected.begin(), E = Selected.end(); I != E; ++I)
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scanSchedRW(*I, RWDefs, RWSet);
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}
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}
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}
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// Collect and sort all SchedReadWrites reachable via tablegen records.
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// More may be inferred later when inferring new SchedClasses from variants.
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void CodeGenSchedModels::collectSchedRW() {
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// Reserve idx=0 for invalid writes/reads.
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SchedWrites.resize(1);
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SchedReads.resize(1);
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SmallPtrSet<Record*, 16> RWSet;
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// Find all SchedReadWrites referenced by instruction defs.
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RecVec SWDefs, SRDefs;
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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E = Target.inst_end(); I != E; ++I) {
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Record *SchedDef = (*I)->TheDef;
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if (!SchedDef->isSubClassOf("Sched"))
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continue;
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RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
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for (RecIter RWI = RWs.begin(), RWE = RWs.end(); RWI != RWE; ++RWI) {
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if ((*RWI)->isSubClassOf("SchedWrite"))
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scanSchedRW(*RWI, SWDefs, RWSet);
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else {
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assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(*RWI, SRDefs, RWSet);
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}
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}
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}
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// Find all ReadWrites referenced by InstRW.
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RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
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for (RecIter OI = InstRWDefs.begin(), OE = InstRWDefs.end(); OI != OE; ++OI) {
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// For all OperandReadWrites.
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RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
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RWI != RWE; ++RWI) {
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if ((*RWI)->isSubClassOf("SchedWrite"))
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scanSchedRW(*RWI, SWDefs, RWSet);
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else {
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assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(*RWI, SRDefs, RWSet);
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}
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}
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}
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// Find all ReadWrites referenced by ItinRW.
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RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
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for (RecIter II = ItinRWDefs.begin(), IE = ItinRWDefs.end(); II != IE; ++II) {
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// For all OperandReadWrites.
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RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites");
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
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RWI != RWE; ++RWI) {
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if ((*RWI)->isSubClassOf("SchedWrite"))
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scanSchedRW(*RWI, SWDefs, RWSet);
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else {
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assert((*RWI)->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
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scanSchedRW(*RWI, SRDefs, RWSet);
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}
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}
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}
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// Sort and add the SchedReadWrites directly referenced by instructions or
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// itinerary resources. Index reads and writes in separate domains.
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std::sort(SWDefs.begin(), SWDefs.end(), LessRecord());
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for (RecIter SWI = SWDefs.begin(), SWE = SWDefs.end(); SWI != SWE; ++SWI) {
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assert(!getSchedRWIdx(*SWI, /*IsRead=*/false) && "duplicate SchedWrite");
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SchedWrites.push_back(CodeGenSchedRW(*SWI));
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}
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std::sort(SRDefs.begin(), SRDefs.end(), LessRecord());
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for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) {
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assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite");
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SchedReads.push_back(CodeGenSchedRW(*SRI));
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}
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// Initialize WriteSequence vectors.
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for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(),
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WE = SchedWrites.end(); WI != WE; ++WI) {
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if (!WI->IsSequence)
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continue;
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findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
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/*IsRead=*/false);
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}
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DEBUG(
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for (unsigned WIdx = 0, WEnd = SchedWrites.size(); WIdx != WEnd; ++WIdx) {
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dbgs() << WIdx << ": ";
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SchedWrites[WIdx].dump();
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dbgs() << '\n';
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}
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for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd; ++RIdx) {
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dbgs() << RIdx << ": ";
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SchedReads[RIdx].dump();
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dbgs() << '\n';
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}
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RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");
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for (RecIter RI = RWDefs.begin(), RE = RWDefs.end();
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RI != RE; ++RI) {
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if (!getSchedRWIdx(*RI, (*RI)->isSubClassOf("SchedRead"))) {
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const std::string &Name = (*RI)->getName();
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if (Name != "NoWrite" && Name != "ReadDefault")
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dbgs() << "Unused SchedReadWrite " << (*RI)->getName() << '\n';
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}
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});
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}
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/// Compute a SchedWrite name from a sequence of writes.
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std::string CodeGenSchedModels::genRWName(const IdxVec& Seq, bool IsRead) {
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std::string Name("(");
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for (IdxIter I = Seq.begin(), E = Seq.end(); I != E; ++I) {
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if (I != Seq.begin())
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Name += '_';
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Name += getSchedRW(*I, IsRead).Name;
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}
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Name += ')';
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return Name;
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}
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unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead,
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unsigned After) const {
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const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
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assert(After < RWVec.size() && "start position out of bounds");
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for (std::vector<CodeGenSchedRW>::const_iterator I = RWVec.begin() + After,
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E = RWVec.end(); I != E; ++I) {
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if (I->TheDef == Def)
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return I - RWVec.begin();
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}
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return 0;
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}
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namespace llvm {
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void splitSchedReadWrites(const RecVec &RWDefs,
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RecVec &WriteDefs, RecVec &ReadDefs) {
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) {
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if ((*RWI)->isSubClassOf("SchedWrite"))
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WriteDefs.push_back(*RWI);
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else {
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assert((*RWI)->isSubClassOf("SchedRead") && "unknown SchedReadWrite");
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ReadDefs.push_back(*RWI);
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}
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}
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}
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} // namespace llvm
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// Split the SchedReadWrites defs and call findRWs for each list.
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void CodeGenSchedModels::findRWs(const RecVec &RWDefs,
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IdxVec &Writes, IdxVec &Reads) const {
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RecVec WriteDefs;
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RecVec ReadDefs;
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splitSchedReadWrites(RWDefs, WriteDefs, ReadDefs);
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findRWs(WriteDefs, Writes, false);
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findRWs(ReadDefs, Reads, true);
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}
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// Call getSchedRWIdx for all elements in a sequence of SchedRW defs.
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void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,
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bool IsRead) const {
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for (RecIter RI = RWDefs.begin(), RE = RWDefs.end(); RI != RE; ++RI) {
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unsigned Idx = getSchedRWIdx(*RI, IsRead);
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assert(Idx && "failed to collect SchedReadWrite");
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RWs.push_back(Idx);
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}
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}
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/// Visit all the instruction definitions for this target to gather and
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/// enumerate the itinerary classes. These are the explicitly specified
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/// SchedClasses. More SchedClasses may be inferred.
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void CodeGenSchedModels::collectSchedClasses() {
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// NoItinerary is always the first class at Idx=0
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SchedClasses.resize(1);
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SchedClasses.back().Name = "NoItinerary";
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SchedClasses.back().ProcIndices.push_back(0);
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SchedClassIdxMap[SchedClasses.back().Name] = 0;
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// Gather and sort all itinerary classes used by instruction descriptions.
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std::vector<Record*> ItinClassList;
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RecVec ItinClassList;
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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E = Target.inst_end(); I != E; ++I) {
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Record *SchedDef = (*I)->TheDef->getValueAsDef("Itinerary");
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Record *ItinDef = (*I)->TheDef->getValueAsDef("Itinerary");
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// Map a new SchedClass with no index.
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if (!SchedClassIdxMap.count(SchedDef->getName())) {
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SchedClassIdxMap[SchedDef->getName()] = 0;
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ItinClassList.push_back(SchedDef);
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if (!SchedClassIdxMap.count(ItinDef->getName())) {
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SchedClassIdxMap[ItinDef->getName()] = 0;
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ItinClassList.push_back(ItinDef);
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}
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}
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// Assign each itinerary class unique number, skipping NoItinerary==0
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@ -61,91 +319,340 @@ void CodeGenSchedModels::CollectSchedClasses() {
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SchedClassIdxMap[ItinDef->getName()] = SchedClasses.size();
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SchedClasses.push_back(CodeGenSchedClass(ItinDef));
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}
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// Infer classes from SchedReadWrite resources listed for each
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// instruction definition that inherits from class Sched.
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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E = Target.inst_end(); I != E; ++I) {
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if (!(*I)->TheDef->isSubClassOf("Sched"))
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continue;
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IdxVec Writes, Reads;
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findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
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// ProcIdx == 0 indicates the class applies to all processors.
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IdxVec ProcIndices(1, 0);
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addSchedClass(Writes, Reads, ProcIndices);
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}
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// Create classes for InstReadWrite defs.
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RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
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std::sort(InstRWDefs.begin(), InstRWDefs.end(), LessRecord());
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for (RecIter OI = InstRWDefs.begin(), OE = InstRWDefs.end(); OI != OE; ++OI)
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createInstRWClass(*OI);
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// TODO: Infer classes from non-itinerary scheduler resources.
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}
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NumInstrSchedClasses = SchedClasses.size();
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// Gather all processor models.
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void CodeGenSchedModels::CollectProcModels() {
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std::vector<Record*> ProcRecords =
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Records.getAllDerivedDefinitions("Processor");
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std::sort(ProcRecords.begin(), ProcRecords.end(), LessRecordFieldName());
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// Reserve space because we can. Reallocation would be ok.
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ProcModels.reserve(ProcRecords.size());
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// For each processor, find a unique machine model.
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for (unsigned i = 0, N = ProcRecords.size(); i < N; ++i)
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addProcModel(ProcRecords[i]);
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}
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// Get a unique processor model based on the defined MachineModel and
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// ProcessorItineraries.
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void CodeGenSchedModels::addProcModel(Record *ProcDef) {
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unsigned Idx = getProcModelIdx(ProcDef);
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if (Idx < ProcModels.size())
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bool EnableDump = false;
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DEBUG(EnableDump = true);
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if (!EnableDump)
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return;
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Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
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Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
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std::string ModelName = ModelDef->getName();
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const std::string &ItinName = ItinsDef->getName();
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bool NoModel = ModelDef->getValueAsBit("NoModel");
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bool hasTopLevelItin = !ItinsDef->getValueAsListOfDefs("IID").empty();
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if (NoModel) {
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// If an itinerary is defined without a machine model, infer a new model.
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if (NoModel && hasTopLevelItin) {
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ModelName = ItinName + "Model";
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ModelDef = NULL;
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for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
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E = Target.inst_end(); I != E; ++I) {
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Record *SchedDef = (*I)->TheDef;
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std::string InstName = (*I)->TheDef->getName();
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if (SchedDef->isSubClassOf("Sched")) {
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IdxVec Writes;
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IdxVec Reads;
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findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
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dbgs() << "SchedRW machine model for " << InstName;
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for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
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dbgs() << " " << SchedWrites[*WI].Name;
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for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI)
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dbgs() << " " << SchedReads[*RI].Name;
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dbgs() << '\n';
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}
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unsigned SCIdx = InstrClassMap.lookup((*I)->TheDef);
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if (SCIdx) {
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const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
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for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end();
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RWI != RWE; ++RWI) {
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const CodeGenProcModel &ProcModel =
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getProcModel((*RWI)->getValueAsDef("SchedModel"));
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dbgs() << "InstrRW on " << ProcModel.ModelName << " for " << InstName;
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IdxVec Writes;
|
||||
IdxVec Reads;
|
||||
findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),
|
||||
Writes, Reads);
|
||||
for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
|
||||
dbgs() << " " << SchedWrites[*WI].Name;
|
||||
for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI)
|
||||
dbgs() << " " << SchedReads[*RI].Name;
|
||||
dbgs() << '\n';
|
||||
}
|
||||
continue;
|
||||
}
|
||||
if (!SchedDef->isSubClassOf("Sched")
|
||||
&& (SchedDef->getValueAsDef("Itinerary")->getName() == "NoItinerary")) {
|
||||
dbgs() << "No machine model for " << (*I)->TheDef->getName() << '\n';
|
||||
}
|
||||
}
|
||||
else {
|
||||
// If a machine model is defined, the itinerary must be defined within it
|
||||
// rather than in the Processor definition itself.
|
||||
assert(!hasTopLevelItin && "Itinerary must be defined in SchedModel");
|
||||
ItinsDef = ModelDef->getValueAsDef("Itineraries");
|
||||
}
|
||||
|
||||
unsigned CodeGenSchedModels::getSchedClassIdx(
|
||||
const RecVec &RWDefs) const {
|
||||
|
||||
IdxVec Writes, Reads;
|
||||
findRWs(RWDefs, Writes, Reads);
|
||||
return findSchedClassIdx(Writes, Reads);
|
||||
}
|
||||
|
||||
/// Find an SchedClass that has been inferred from a per-operand list of
|
||||
/// SchedWrites and SchedReads.
|
||||
unsigned CodeGenSchedModels::findSchedClassIdx(const IdxVec &Writes,
|
||||
const IdxVec &Reads) const {
|
||||
for (SchedClassIter I = schedClassBegin(), E = schedClassEnd(); I != E; ++I) {
|
||||
// Classes with InstRWs may have the same Writes/Reads as a class originally
|
||||
// produced by a SchedRW definition. We need to be able to recover the
|
||||
// original class index for processors that don't match any InstRWs.
|
||||
if (I->ItinClassDef || !I->InstRWs.empty())
|
||||
continue;
|
||||
|
||||
if (I->Writes == Writes && I->Reads == Reads) {
|
||||
return I - schedClassBegin();
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
ProcModelMap[getProcModelKey(ProcDef)]= ProcModels.size();
|
||||
// Get the SchedClass index for an instruction.
|
||||
unsigned CodeGenSchedModels::getSchedClassIdx(
|
||||
const CodeGenInstruction &Inst) const {
|
||||
|
||||
ProcModels.push_back(CodeGenProcModel(ModelName, ModelDef, ItinsDef));
|
||||
unsigned SCIdx = InstrClassMap.lookup(Inst.TheDef);
|
||||
if (SCIdx)
|
||||
return SCIdx;
|
||||
|
||||
std::vector<Record*> ItinRecords = ItinsDef->getValueAsListOfDefs("IID");
|
||||
CollectProcItin(ProcModels.back(), ItinRecords);
|
||||
// If this opcode isn't mapped by the subtarget fallback to the instruction
|
||||
// definition's SchedRW or ItinDef values.
|
||||
if (Inst.TheDef->isSubClassOf("Sched")) {
|
||||
RecVec RWs = Inst.TheDef->getValueAsListOfDefs("SchedRW");
|
||||
return getSchedClassIdx(RWs);
|
||||
}
|
||||
Record *ItinDef = Inst.TheDef->getValueAsDef("Itinerary");
|
||||
assert(SchedClassIdxMap.count(ItinDef->getName()) && "missing ItinClass");
|
||||
unsigned Idx = SchedClassIdxMap.lookup(ItinDef->getName());
|
||||
assert(Idx <= NumItineraryClasses && "bad ItinClass index");
|
||||
return Idx;
|
||||
}
|
||||
|
||||
std::string CodeGenSchedModels::createSchedClassName(
|
||||
const IdxVec &OperWrites, const IdxVec &OperReads) {
|
||||
|
||||
std::string Name;
|
||||
for (IdxIter WI = OperWrites.begin(), WE = OperWrites.end(); WI != WE; ++WI) {
|
||||
if (WI != OperWrites.begin())
|
||||
Name += '_';
|
||||
Name += SchedWrites[*WI].Name;
|
||||
}
|
||||
for (IdxIter RI = OperReads.begin(), RE = OperReads.end(); RI != RE; ++RI) {
|
||||
Name += '_';
|
||||
Name += SchedReads[*RI].Name;
|
||||
}
|
||||
return Name;
|
||||
}
|
||||
|
||||
std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {
|
||||
|
||||
std::string Name;
|
||||
for (RecIter I = InstDefs.begin(), E = InstDefs.end(); I != E; ++I) {
|
||||
if (I != InstDefs.begin())
|
||||
Name += '_';
|
||||
Name += (*I)->getName();
|
||||
}
|
||||
return Name;
|
||||
}
|
||||
|
||||
/// Add an inferred sched class from a per-operand list of SchedWrites and
|
||||
/// SchedReads. ProcIndices contains the set of IDs of processors that may
|
||||
/// utilize this class.
|
||||
unsigned CodeGenSchedModels::addSchedClass(const IdxVec &OperWrites,
|
||||
const IdxVec &OperReads,
|
||||
const IdxVec &ProcIndices)
|
||||
{
|
||||
assert(!ProcIndices.empty() && "expect at least one ProcIdx");
|
||||
|
||||
unsigned Idx = findSchedClassIdx(OperWrites, OperReads);
|
||||
if (Idx) {
|
||||
IdxVec PI;
|
||||
std::set_union(SchedClasses[Idx].ProcIndices.begin(),
|
||||
SchedClasses[Idx].ProcIndices.end(),
|
||||
ProcIndices.begin(), ProcIndices.end(),
|
||||
std::back_inserter(PI));
|
||||
SchedClasses[Idx].ProcIndices.swap(PI);
|
||||
return Idx;
|
||||
}
|
||||
Idx = SchedClasses.size();
|
||||
SchedClasses.resize(Idx+1);
|
||||
CodeGenSchedClass &SC = SchedClasses.back();
|
||||
SC.Name = createSchedClassName(OperWrites, OperReads);
|
||||
SC.Writes = OperWrites;
|
||||
SC.Reads = OperReads;
|
||||
SC.ProcIndices = ProcIndices;
|
||||
|
||||
return Idx;
|
||||
}
|
||||
|
||||
// Create classes for each set of opcodes that are in the same InstReadWrite
|
||||
// definition across all processors.
|
||||
void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
|
||||
// ClassInstrs will hold an entry for each subset of Instrs in InstRWDef that
|
||||
// intersects with an existing class via a previous InstRWDef. Instrs that do
|
||||
// not intersect with an existing class refer back to their former class as
|
||||
// determined from ItinDef or SchedRW.
|
||||
SmallVector<std::pair<unsigned, SmallVector<Record *, 8> >, 4> ClassInstrs;
|
||||
// Sort Instrs into sets.
|
||||
RecVec InstDefs = InstRWDef->getValueAsListOfDefs("Instrs");
|
||||
std::sort(InstDefs.begin(), InstDefs.end(), LessRecord());
|
||||
for (RecIter I = InstDefs.begin(), E = InstDefs.end(); I != E; ++I) {
|
||||
unsigned SCIdx = 0;
|
||||
InstClassMapTy::const_iterator Pos = InstrClassMap.find(*I);
|
||||
if (Pos != InstrClassMap.end())
|
||||
SCIdx = Pos->second;
|
||||
else {
|
||||
// This instruction has not been mapped yet. Get the original class. All
|
||||
// instructions in the same InstrRW class must be from the same original
|
||||
// class because that is the fall-back class for other processors.
|
||||
Record *ItinDef = (*I)->getValueAsDef("Itinerary");
|
||||
SCIdx = SchedClassIdxMap.lookup(ItinDef->getName());
|
||||
if (!SCIdx && (*I)->isSubClassOf("Sched"))
|
||||
SCIdx = getSchedClassIdx((*I)->getValueAsListOfDefs("SchedRW"));
|
||||
}
|
||||
unsigned CIdx = 0, CEnd = ClassInstrs.size();
|
||||
for (; CIdx != CEnd; ++CIdx) {
|
||||
if (ClassInstrs[CIdx].first == SCIdx)
|
||||
break;
|
||||
}
|
||||
if (CIdx == CEnd) {
|
||||
ClassInstrs.resize(CEnd + 1);
|
||||
ClassInstrs[CIdx].first = SCIdx;
|
||||
}
|
||||
ClassInstrs[CIdx].second.push_back(*I);
|
||||
}
|
||||
// For each set of Instrs, create a new class if necessary, and map or remap
|
||||
// the Instrs to it.
|
||||
unsigned CIdx = 0, CEnd = ClassInstrs.size();
|
||||
for (; CIdx != CEnd; ++CIdx) {
|
||||
unsigned OldSCIdx = ClassInstrs[CIdx].first;
|
||||
ArrayRef<Record*> InstDefs = ClassInstrs[CIdx].second;
|
||||
// If the all instrs in the current class are accounted for, then leave
|
||||
// them mapped to their old class.
|
||||
if (SchedClasses[OldSCIdx].InstRWs.size() == InstDefs.size()) {
|
||||
assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
|
||||
"expected a generic SchedClass");
|
||||
continue;
|
||||
}
|
||||
unsigned SCIdx = SchedClasses.size();
|
||||
SchedClasses.resize(SCIdx+1);
|
||||
CodeGenSchedClass &SC = SchedClasses.back();
|
||||
SC.Name = createSchedClassName(InstDefs);
|
||||
// Preserve ItinDef and Writes/Reads for processors without an InstRW entry.
|
||||
SC.ItinClassDef = SchedClasses[OldSCIdx].ItinClassDef;
|
||||
SC.Writes = SchedClasses[OldSCIdx].Writes;
|
||||
SC.Reads = SchedClasses[OldSCIdx].Reads;
|
||||
SC.ProcIndices.push_back(0);
|
||||
// Map each Instr to this new class.
|
||||
// Note that InstDefs may be a smaller list than InstRWDef's "Instrs".
|
||||
for (ArrayRef<Record*>::const_iterator
|
||||
II = InstDefs.begin(), IE = InstDefs.end(); II != IE; ++II) {
|
||||
unsigned OldSCIdx = InstrClassMap[*II];
|
||||
if (OldSCIdx) {
|
||||
SC.InstRWs.insert(SC.InstRWs.end(),
|
||||
SchedClasses[OldSCIdx].InstRWs.begin(),
|
||||
SchedClasses[OldSCIdx].InstRWs.end());
|
||||
}
|
||||
InstrClassMap[*II] = SCIdx;
|
||||
}
|
||||
SC.InstRWs.push_back(InstRWDef);
|
||||
}
|
||||
}
|
||||
|
||||
// Gather the processor itineraries.
|
||||
void CodeGenSchedModels::CollectProcItin(CodeGenProcModel &ProcModel,
|
||||
std::vector<Record*> ItinRecords) {
|
||||
// Skip empty itinerary.
|
||||
if (ItinRecords.empty())
|
||||
return;
|
||||
|
||||
HasProcItineraries = true;
|
||||
|
||||
ProcModel.ItinDefList.resize(NumItineraryClasses+1);
|
||||
|
||||
// Insert each itinerary data record in the correct position within
|
||||
// the processor model's ItinDefList.
|
||||
for (unsigned i = 0, N = ItinRecords.size(); i < N; i++) {
|
||||
Record *ItinData = ItinRecords[i];
|
||||
Record *ItinDef = ItinData->getValueAsDef("TheClass");
|
||||
if (!SchedClassIdxMap.count(ItinDef->getName())) {
|
||||
DEBUG(dbgs() << ProcModel.ItinsDef->getName()
|
||||
<< " has unused itinerary class " << ItinDef->getName() << '\n');
|
||||
void CodeGenSchedModels::collectProcItins() {
|
||||
for (std::vector<CodeGenProcModel>::iterator PI = ProcModels.begin(),
|
||||
PE = ProcModels.end(); PI != PE; ++PI) {
|
||||
CodeGenProcModel &ProcModel = *PI;
|
||||
RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");
|
||||
// Skip empty itinerary.
|
||||
if (ItinRecords.empty())
|
||||
continue;
|
||||
|
||||
ProcModel.ItinDefList.resize(NumItineraryClasses+1);
|
||||
|
||||
// Insert each itinerary data record in the correct position within
|
||||
// the processor model's ItinDefList.
|
||||
for (unsigned i = 0, N = ItinRecords.size(); i < N; i++) {
|
||||
Record *ItinData = ItinRecords[i];
|
||||
Record *ItinDef = ItinData->getValueAsDef("TheClass");
|
||||
if (!SchedClassIdxMap.count(ItinDef->getName())) {
|
||||
DEBUG(dbgs() << ProcModel.ItinsDef->getName()
|
||||
<< " has unused itinerary class " << ItinDef->getName() << '\n');
|
||||
continue;
|
||||
}
|
||||
assert(SchedClassIdxMap.count(ItinDef->getName()) && "missing ItinClass");
|
||||
unsigned Idx = SchedClassIdxMap.lookup(ItinDef->getName());
|
||||
assert(Idx <= NumItineraryClasses && "bad ItinClass index");
|
||||
ProcModel.ItinDefList[Idx] = ItinData;
|
||||
}
|
||||
ProcModel.ItinDefList[getItinClassIdx(ItinDef)] = ItinData;
|
||||
// Check for missing itinerary entries.
|
||||
assert(!ProcModel.ItinDefList[0] && "NoItinerary class can't have rec");
|
||||
DEBUG(
|
||||
for (unsigned i = 1, N = ProcModel.ItinDefList.size(); i < N; ++i) {
|
||||
if (!ProcModel.ItinDefList[i])
|
||||
dbgs() << ProcModel.ItinsDef->getName()
|
||||
<< " missing itinerary for class "
|
||||
<< SchedClasses[i].Name << '\n';
|
||||
});
|
||||
}
|
||||
#ifndef NDEBUG
|
||||
// Check for missing itinerary entries.
|
||||
assert(!ProcModel.ItinDefList[0] && "NoItinerary class can't have rec");
|
||||
for (unsigned i = 1, N = ProcModel.ItinDefList.size(); i < N; ++i) {
|
||||
if (!ProcModel.ItinDefList[i])
|
||||
DEBUG(dbgs() << ProcModel.ItinsDef->getName()
|
||||
<< " missing itinerary for class " << SchedClasses[i].Name << '\n');
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
// Gather the read/write types for each itinerary class.
|
||||
void CodeGenSchedModels::collectProcItinRW() {
|
||||
RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
|
||||
std::sort(ItinRWDefs.begin(), ItinRWDefs.end(), LessRecord());
|
||||
for (RecIter II = ItinRWDefs.begin(), IE = ItinRWDefs.end(); II != IE; ++II) {
|
||||
if (!(*II)->getValueInit("SchedModel")->isComplete())
|
||||
throw TGError((*II)->getLoc(), "SchedModel is undefined");
|
||||
Record *ModelDef = (*II)->getValueAsDef("SchedModel");
|
||||
ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
|
||||
if (I == ProcModelMap.end()) {
|
||||
throw TGError((*II)->getLoc(), "Undefined SchedMachineModel "
|
||||
+ ModelDef->getName());
|
||||
}
|
||||
ProcModels[I->second].ItinRWDefs.push_back(*II);
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
void CodeGenProcModel::dump() const {
|
||||
dbgs() << Index << ": " << ModelName << " "
|
||||
<< (ModelDef ? ModelDef->getName() : "inferred") << " "
|
||||
<< (ItinsDef ? ItinsDef->getName() : "no itinerary") << '\n';
|
||||
}
|
||||
|
||||
void CodeGenSchedRW::dump() const {
|
||||
dbgs() << Name << (IsVariadic ? " (V) " : " ");
|
||||
if (IsSequence) {
|
||||
dbgs() << "(";
|
||||
dumpIdxVec(Sequence);
|
||||
dbgs() << ")";
|
||||
}
|
||||
}
|
||||
|
||||
void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
|
||||
dbgs() << "SCHEDCLASS " << Name << '\n'
|
||||
<< " Writes: ";
|
||||
for (unsigned i = 0, N = Writes.size(); i < N; ++i) {
|
||||
SchedModels->getSchedWrite(Writes[i]).dump();
|
||||
if (i < N-1) {
|
||||
dbgs() << '\n';
|
||||
dbgs().indent(10);
|
||||
}
|
||||
}
|
||||
dbgs() << "\n Reads: ";
|
||||
for (unsigned i = 0, N = Reads.size(); i < N; ++i) {
|
||||
SchedModels->getSchedRead(Reads[i]).dump();
|
||||
if (i < N-1) {
|
||||
dbgs() << '\n';
|
||||
dbgs().indent(10);
|
||||
}
|
||||
}
|
||||
dbgs() << "\n ProcIdx: "; dumpIdxVec(ProcIndices); dbgs() << '\n';
|
||||
}
|
||||
#endif // NDEBUG
|
||||
|
||||
@ -23,21 +23,112 @@
|
||||
namespace llvm {
|
||||
|
||||
class CodeGenTarget;
|
||||
class CodeGenSchedModels;
|
||||
class CodeGenInstruction;
|
||||
|
||||
// Scheduling class.
|
||||
//
|
||||
// Each instruction description will be mapped to a scheduling class. It may be
|
||||
// an explicitly defined itinerary class, or an inferred class in which case
|
||||
// ItinClassDef == NULL.
|
||||
typedef std::vector<Record*> RecVec;
|
||||
typedef std::vector<Record*>::const_iterator RecIter;
|
||||
|
||||
typedef std::vector<unsigned> IdxVec;
|
||||
typedef std::vector<unsigned>::const_iterator IdxIter;
|
||||
|
||||
void splitSchedReadWrites(const RecVec &RWDefs,
|
||||
RecVec &WriteDefs, RecVec &ReadDefs);
|
||||
|
||||
/// We have two kinds of SchedReadWrites. Explicitly defined and inferred
|
||||
/// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
|
||||
/// may not be empty. TheDef is null for inferred sequences, and Sequence must
|
||||
/// be nonempty.
|
||||
///
|
||||
/// IsVariadic controls whether the variants are expanded into multiple operands
|
||||
/// or a sequence of writes on one operand.
|
||||
struct CodeGenSchedRW {
|
||||
std::string Name;
|
||||
Record *TheDef;
|
||||
bool HasVariants;
|
||||
bool IsVariadic;
|
||||
bool IsSequence;
|
||||
IdxVec Sequence;
|
||||
|
||||
CodeGenSchedRW(): TheDef(0), HasVariants(false), IsVariadic(false),
|
||||
IsSequence(false) {}
|
||||
CodeGenSchedRW(Record *Def): TheDef(Def), IsVariadic(false) {
|
||||
Name = Def->getName();
|
||||
HasVariants = Def->isSubClassOf("SchedVariant");
|
||||
if (HasVariants)
|
||||
IsVariadic = Def->getValueAsBit("Variadic");
|
||||
|
||||
// Read records don't currently have sequences, but it can be easily
|
||||
// added. Note that implicit Reads (from ReadVariant) may have a Sequence
|
||||
// (but no record).
|
||||
IsSequence = Def->isSubClassOf("WriteSequence");
|
||||
}
|
||||
|
||||
CodeGenSchedRW(const IdxVec &Seq, const std::string &Name):
|
||||
Name(Name), TheDef(0), HasVariants(false), IsVariadic(false),
|
||||
IsSequence(true), Sequence(Seq) {
|
||||
assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
|
||||
}
|
||||
|
||||
bool isValid() const {
|
||||
assert((!HasVariants || TheDef) && "Variant write needs record def");
|
||||
assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
|
||||
assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
|
||||
assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
|
||||
return TheDef || !Sequence.empty();
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
void dump() const;
|
||||
#endif
|
||||
};
|
||||
|
||||
/// Scheduling class.
|
||||
///
|
||||
/// Each instruction description will be mapped to a scheduling class. There are
|
||||
/// four types of classes:
|
||||
///
|
||||
/// 1) An explicitly defined itinerary class with ItinClassDef set.
|
||||
/// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
|
||||
///
|
||||
/// 2) An implied class with a list of SchedWrites and SchedReads that are
|
||||
/// defined in an instruction definition and which are common across all
|
||||
/// subtargets. ProcIndices contains 0 for any processor.
|
||||
///
|
||||
/// 3) An implied class with a list of InstRW records that map instructions to
|
||||
/// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
|
||||
/// instructions to this class. ProcIndices contains all the processors that
|
||||
/// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
|
||||
/// still be defined for processors with no InstRW entry.
|
||||
///
|
||||
/// 4) An inferred class represents a variant of another class that may be
|
||||
/// resolved at runtime. ProcIndices contains the set of processors that may
|
||||
/// require the class. ProcIndices are propagated through SchedClasses as
|
||||
/// variants are expanded. Multiple SchedClasses may be inferred from an
|
||||
/// itinerary class. Each inherits the processor index from the ItinRW record
|
||||
/// that mapped the itinerary class to the variant Writes or Reads.
|
||||
struct CodeGenSchedClass {
|
||||
std::string Name;
|
||||
unsigned Index;
|
||||
Record *ItinClassDef;
|
||||
|
||||
CodeGenSchedClass(): Index(0), ItinClassDef(0) {}
|
||||
CodeGenSchedClass(Record *rec): Index(0), ItinClassDef(rec) {
|
||||
IdxVec Writes;
|
||||
IdxVec Reads;
|
||||
// Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
|
||||
IdxVec ProcIndices;
|
||||
|
||||
// InstReadWrite records associated with this class. Any Instrs that the
|
||||
// definitions refer to that are not mapped to this class should be ignored.
|
||||
RecVec InstRWs;
|
||||
|
||||
CodeGenSchedClass(): ItinClassDef(0) {}
|
||||
CodeGenSchedClass(Record *rec): ItinClassDef(rec) {
|
||||
Name = rec->getName();
|
||||
ProcIndices.push_back(0);
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
void dump(const CodeGenSchedModels *SchedModels) const;
|
||||
#endif
|
||||
};
|
||||
|
||||
// Processor model.
|
||||
@ -55,28 +146,53 @@ struct CodeGenSchedClass {
|
||||
//
|
||||
// ItinDefList orders this processor's InstrItinData records by SchedClass idx.
|
||||
struct CodeGenProcModel {
|
||||
unsigned Index;
|
||||
std::string ModelName;
|
||||
Record *ModelDef;
|
||||
Record *ItinsDef;
|
||||
|
||||
// Array of InstrItinData records indexed by CodeGenSchedClass::Index.
|
||||
// The list is empty if the subtarget has no itineraries.
|
||||
std::vector<Record *> ItinDefList;
|
||||
// Derived members...
|
||||
|
||||
CodeGenProcModel(const std::string &Name, Record *MDef, Record *IDef):
|
||||
ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
|
||||
// Array of InstrItinData records indexed by a CodeGenSchedClass index.
|
||||
// This list is empty if the Processor has no value for Itineraries.
|
||||
// Initialized by collectProcItins().
|
||||
RecVec ItinDefList;
|
||||
|
||||
// Map itinerary classes to per-operand resources.
|
||||
// This list is empty if no ItinRW refers to this Processor.
|
||||
RecVec ItinRWDefs;
|
||||
|
||||
CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
|
||||
Record *IDef) :
|
||||
Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
|
||||
|
||||
#ifndef NDEBUG
|
||||
void dump() const;
|
||||
#endif
|
||||
};
|
||||
|
||||
// Top level container for machine model data.
|
||||
/// Top level container for machine model data.
|
||||
class CodeGenSchedModels {
|
||||
RecordKeeper &Records;
|
||||
const CodeGenTarget &Target;
|
||||
|
||||
// List of unique processor models.
|
||||
std::vector<CodeGenProcModel> ProcModels;
|
||||
|
||||
// Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
|
||||
typedef DenseMap<Record*, unsigned> ProcModelMapTy;
|
||||
ProcModelMapTy ProcModelMap;
|
||||
|
||||
// Per-operand SchedReadWrite types.
|
||||
std::vector<CodeGenSchedRW> SchedWrites;
|
||||
std::vector<CodeGenSchedRW> SchedReads;
|
||||
|
||||
// List of unique SchedClasses.
|
||||
std::vector<CodeGenSchedClass> SchedClasses;
|
||||
|
||||
// Map SchedClass name to itinerary index.
|
||||
// These are either explicit itinerary classes or inferred classes.
|
||||
// These are either explicit itinerary classes or classes implied by
|
||||
// instruction definitions with SchedReadWrite lists.
|
||||
StringMap<unsigned> SchedClassIdxMap;
|
||||
|
||||
// SchedClass indices 1 up to and including NumItineraryClasses identify
|
||||
@ -84,22 +200,68 @@ class CodeGenSchedModels {
|
||||
// definitions. NoItinerary always has index 0 regardless of whether it is
|
||||
// explicitly referenced.
|
||||
//
|
||||
// Any inferred SchedClass have a index greater than NumItineraryClasses.
|
||||
// Any implied SchedClass has an index greater than NumItineraryClasses.
|
||||
unsigned NumItineraryClasses;
|
||||
|
||||
// List of unique processor models.
|
||||
std::vector<CodeGenProcModel> ProcModels;
|
||||
// Any inferred SchedClass has an index greater than NumInstrSchedClassses.
|
||||
unsigned NumInstrSchedClasses;
|
||||
|
||||
// Map Processor's MachineModel + ProcItin fields to a CodeGenProcModel index.
|
||||
typedef DenseMap<std::pair<Record*, Record*>, unsigned> ProcModelMapTy;
|
||||
ProcModelMapTy ProcModelMap;
|
||||
|
||||
// True if any processors have nonempty itineraries.
|
||||
bool HasProcItineraries;
|
||||
// Map Instruction to SchedClass index. Only for Instructions mentioned in
|
||||
// OpReadWrites.
|
||||
typedef DenseMap<Record*, unsigned> InstClassMapTy;
|
||||
InstClassMapTy InstrClassMap;
|
||||
|
||||
public:
|
||||
CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
|
||||
|
||||
Record *getModelOrItinDef(Record *ProcDef) const {
|
||||
Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
|
||||
Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
|
||||
if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
|
||||
assert(ModelDef->getValueAsBit("NoModel")
|
||||
&& "Itineraries must be defined within SchedMachineModel");
|
||||
return ItinsDef;
|
||||
}
|
||||
return ModelDef;
|
||||
}
|
||||
|
||||
const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
|
||||
Record *ModelDef = getModelOrItinDef(ProcDef);
|
||||
ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
|
||||
assert(I != ProcModelMap.end() && "missing machine model");
|
||||
return ProcModels[I->second];
|
||||
}
|
||||
|
||||
const CodeGenProcModel &getProcModel(Record *ModelDef) const {
|
||||
ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
|
||||
assert(I != ProcModelMap.end() && "missing machine model");
|
||||
return ProcModels[I->second];
|
||||
}
|
||||
|
||||
// Iterate over the unique processor models.
|
||||
typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
|
||||
ProcIter procModelBegin() const { return ProcModels.begin(); }
|
||||
ProcIter procModelEnd() const { return ProcModels.end(); }
|
||||
|
||||
// Get a SchedWrite from its index.
|
||||
const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
|
||||
assert(Idx < SchedWrites.size() && "bad SchedWrite index");
|
||||
assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
|
||||
return SchedWrites[Idx];
|
||||
}
|
||||
// Get a SchedWrite from its index.
|
||||
const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
|
||||
assert(Idx < SchedReads.size() && "bad SchedRead index");
|
||||
assert(SchedReads[Idx].isValid() && "invalid SchedRead");
|
||||
return SchedReads[Idx];
|
||||
}
|
||||
|
||||
const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
|
||||
return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
|
||||
}
|
||||
|
||||
unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
|
||||
|
||||
// Check if any instructions are assigned to an explicit itinerary class other
|
||||
// than NoItinerary.
|
||||
bool hasItineraryClasses() const { return NumItineraryClasses > 0; }
|
||||
@ -111,7 +273,11 @@ public:
|
||||
}
|
||||
|
||||
// Get a SchedClass from its index.
|
||||
const CodeGenSchedClass &getSchedClass(unsigned Idx) {
|
||||
CodeGenSchedClass &getSchedClass(unsigned Idx) {
|
||||
assert(Idx < SchedClasses.size() && "bad SchedClass index");
|
||||
return SchedClasses[Idx];
|
||||
}
|
||||
const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
|
||||
assert(Idx < SchedClasses.size() && "bad SchedClass index");
|
||||
return SchedClasses[Idx];
|
||||
}
|
||||
@ -125,46 +291,52 @@ public:
|
||||
return Idx;
|
||||
}
|
||||
|
||||
bool hasProcessorItineraries() const {
|
||||
return HasProcItineraries;
|
||||
// Get the SchedClass index for an instruction. Instructions with no
|
||||
// itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
|
||||
// for NoItinerary.
|
||||
unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
|
||||
|
||||
unsigned getSchedClassIdx(const RecVec &RWDefs) const;
|
||||
|
||||
unsigned getSchedClassIdxForItin(const Record *ItinDef) {
|
||||
return SchedClassIdxMap[ItinDef->getName()];
|
||||
}
|
||||
|
||||
// Get an existing machine model for a processor definition.
|
||||
const CodeGenProcModel &getProcModel(Record *ProcDef) const {
|
||||
unsigned idx = getProcModelIdx(ProcDef);
|
||||
assert(idx < ProcModels.size() && "missing machine model");
|
||||
return ProcModels[idx];
|
||||
}
|
||||
typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter;
|
||||
SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
|
||||
SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
|
||||
|
||||
// Iterate over the unique processor models.
|
||||
typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
|
||||
ProcIter procModelBegin() const { return ProcModels.begin(); }
|
||||
ProcIter procModelEnd() const { return ProcModels.end(); }
|
||||
void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
|
||||
void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
|
||||
|
||||
unsigned addSchedClass(const IdxVec &OperWrites, const IdxVec &OperReads,
|
||||
const IdxVec &ProcIndices);
|
||||
|
||||
unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
|
||||
|
||||
unsigned findSchedClassIdx(const IdxVec &Writes, const IdxVec &Reads) const;
|
||||
|
||||
private:
|
||||
// Get a key that can uniquely identify a machine model.
|
||||
ProcModelMapTy::key_type getProcModelKey(Record *ProcDef) const {
|
||||
Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
|
||||
Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
|
||||
return std::make_pair(ModelDef, ItinsDef);
|
||||
}
|
||||
|
||||
// Get the unique index of a machine model.
|
||||
unsigned getProcModelIdx(Record *ProcDef) const {
|
||||
ProcModelMapTy::const_iterator I =
|
||||
ProcModelMap.find(getProcModelKey(ProcDef));
|
||||
if (I == ProcModelMap.end())
|
||||
return ProcModels.size();
|
||||
return I->second;
|
||||
}
|
||||
void collectProcModels();
|
||||
|
||||
// Initialize a new processor model if it is unique.
|
||||
void addProcModel(Record *ProcDef);
|
||||
|
||||
void CollectSchedClasses();
|
||||
void CollectProcModels();
|
||||
void CollectProcItin(CodeGenProcModel &ProcModel,
|
||||
std::vector<Record*> ItinRecords);
|
||||
void collectSchedRW();
|
||||
|
||||
std::string genRWName(const IdxVec& Seq, bool IsRead);
|
||||
unsigned findRWForSequence(const IdxVec &Seq, bool IsRead);
|
||||
|
||||
void collectSchedClasses();
|
||||
|
||||
std::string createSchedClassName(const IdxVec &OperWrites,
|
||||
const IdxVec &OperReads);
|
||||
std::string createSchedClassName(const RecVec &InstDefs);
|
||||
void createInstRWClass(Record *InstRWDef);
|
||||
|
||||
void collectProcItins();
|
||||
|
||||
void collectProcItinRW();
|
||||
};
|
||||
|
||||
} // namespace llvm
|
||||
|
||||
@ -521,7 +521,7 @@ EmitItineraries(raw_ostream &OS,
|
||||
std::vector<std::vector<InstrItinerary> >::iterator
|
||||
ProcItinListsIter = ProcItinLists.begin();
|
||||
for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
|
||||
PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
|
||||
PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
|
||||
|
||||
Record *ItinsDef = PI->ItinsDef;
|
||||
if (!ItinsDefSet.insert(ItinsDef))
|
||||
@ -532,7 +532,7 @@ EmitItineraries(raw_ostream &OS,
|
||||
|
||||
// Get the itinerary list for the processor.
|
||||
assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
|
||||
std::vector<InstrItinerary> &ItinList = *ProcItinListsIter++;
|
||||
std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
|
||||
|
||||
OS << "\n";
|
||||
OS << "static const llvm::InstrItinerary ";
|
||||
@ -621,7 +621,7 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
|
||||
|
||||
const std::string &Name = Processor->getValueAsString("Name");
|
||||
const std::string &ProcModelName =
|
||||
SchedModels.getProcModel(Processor).ModelName;
|
||||
SchedModels.getModelForProc(Processor).ModelName;
|
||||
|
||||
// Emit as { "cpu", procinit },
|
||||
OS << " { "
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user