From 488f228a4f240bfa1153f9cc96dab3d7861d02b2 Mon Sep 17 00:00:00 2001 From: Juergen Ributzka Date: Mon, 15 Sep 2014 23:40:10 +0000 Subject: [PATCH] [FastISel][AArch64] Allow handling of vectors during return lowering for little endian machines. Allow handling of vectors during return lowering at least for little endian machines. This was restricted in r208200 to fix it for big endian machines (according to the comment), but it also disabled it for little endian too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217846 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64FastISel.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/lib/Target/AArch64/AArch64FastISel.cpp b/lib/Target/AArch64/AArch64FastISel.cpp index 07c84cdda5d..619dfd66d1c 100644 --- a/lib/Target/AArch64/AArch64FastISel.cpp +++ b/lib/Target/AArch64/AArch64FastISel.cpp @@ -2871,11 +2871,14 @@ bool AArch64FastISel::selectRet(const Instruction *I) { const Value *RV = Ret->getOperand(0); // Don't bother handling odd stuff for now. - if (VA.getLocInfo() != CCValAssign::Full) + if ((VA.getLocInfo() != CCValAssign::Full) && + (VA.getLocInfo() != CCValAssign::BCvt)) return false; + // Only handle register returns for now. if (!VA.isRegLoc()) return false; + unsigned Reg = getRegForValue(RV); if (Reg == 0) return false; @@ -2891,12 +2894,14 @@ bool AArch64FastISel::selectRet(const Instruction *I) { return false; // Vectors (of > 1 lane) in big endian need tricky handling. - if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1) + if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 && + !Subtarget->isLittleEndian()) return false; MVT RVVT = RVEVT.getSimpleVT(); if (RVVT == MVT::f128) return false; + MVT DestVT = VA.getValVT(); // Special handling for extended integers. if (RVVT != DestVT) {