Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27201 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

@@ -553,14 +553,16 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     break;
   }
     
-  case ISD::INTRINSIC: {
+  case ISD::INTRINSIC_W_CHAIN:
+  case ISD::INTRINSIC_WO_CHAIN:
+  case ISD::INTRINSIC_VOID: {
     std::vector<SDOperand> Ops;
     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
       Ops.push_back(LegalizeOp(Node->getOperand(i)));
     Result = DAG.UpdateNodeOperands(Result, Ops);
     
     // Allow the target to custom lower its intrinsics if it wants to.
-    if (TLI.getOperationAction(ISD::INTRINSIC, MVT::Other) == 
+    if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 
         TargetLowering::Custom) {
       Tmp3 = TLI.LowerOperation(Result, DAG);
       if (Tmp3.Val) Result = Tmp3;

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -2689,9 +2689,13 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::FrameIndex:    return "FrameIndex";
   case ISD::ConstantPool:  return "ConstantPool";
   case ISD::ExternalSymbol: return "ExternalSymbol";
-  case ISD::INTRINSIC: {
+  case ISD::INTRINSIC_WO_CHAIN: {
-    bool hasChain = getOperand(0).getValueType() == MVT::Other;
+    unsigned IID = cast<ConstantSDNode>(getOperand(0))->getValue();
-    unsigned IID = cast<ConstantSDNode>(getOperand(hasChain))->getValue();
+    return Intrinsic::getName((Intrinsic::ID)IID);
+  }
+  case ISD::INTRINSIC_VOID:
+  case ISD::INTRINSIC_W_CHAIN: {
+    unsigned IID = cast<ConstantSDNode>(getOperand(1))->getValue();
     return Intrinsic::getName((Intrinsic::ID)IID);
   }
 

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -1261,8 +1261,14 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
     VTs.push_back(MVT::Other);
 
   // Create the node.
-  SDOperand Result = DAG.getNode(ISD::INTRINSIC, VTs, Ops);
+  SDOperand Result;
-  
+  if (!HasChain)
+    Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
+  else if (I.getType() != Type::VoidTy)
+    Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
+  else
+    Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
+
   if (HasChain)
     DAG.setRoot(Result.getValue(Result.Val->getNumValues()-1));
   if (I.getType() != Type::VoidTy) {

lib/Target/PowerPC/PPCISelLowering.cpp

@@ -138,7 +138,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
   
   // We want to custom lower some of our intrinsics.
-  setOperationAction(ISD::INTRINSIC         , MVT::Other, Custom);
+  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   
   if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
     // They also have instructions for converting between i64 and fp.
@@ -752,7 +752,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     SDOperand VPermMask =DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
     return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
   }
-  case ISD::INTRINSIC: {
+  case ISD::INTRINSIC_WO_CHAIN: {
     bool HasChain = Op.getOperand(0).getValueType() == MVT::Other;
     unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(HasChain))->getValue();
     

lib/Target/PowerPC/PPCInstrAltivec.td

@@ -89,15 +89,15 @@ def LVSR : XForm_1<31,  38, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
                    []>, PPC970_Unit_LSU;
 
 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {   // Stores.
-def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
+def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
-                   "stvebx $rS, $rA, $rB", LdStGeneral,
+                   "stvebx $rS, $dst", LdStGeneral,
-                   []>;
+                   [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
-def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
+def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
-                   "stvehx $rS, $rA, $rB", LdStGeneral,
+                   "stvehx $rS, $dst", LdStGeneral,
-                   []>;
+                   [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
-def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
+def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
-                   "stvewx $rS, $rA, $rB", LdStGeneral,
+                   "stvewx $rS, $dst", LdStGeneral,
-                   []>;
+                   [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
 def STVX  : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
                    "stvx $rS, $dst", LdStGeneral,
                    [(store (v4f32 VRRC:$rS), xoaddr:$dst)]>;

lib/Target/TargetSelectionDAG.td

@@ -313,13 +313,13 @@ def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
 
 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
 // these internally.  Don't reference these directly.
-def intrinsic_void : SDNode<"ISD::INTRINSIC", 
+def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 
                             SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
                             [SDNPHasChain]>;
-def intrinsic_w_chain : SDNode<"ISD::INTRINSIC", 
+def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 
                                SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
                                [SDNPHasChain]>;
-def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC", 
+def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 
                                 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;