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R600: Add pattern for the BFI_INT instruction

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-04-19 02:11:06 +00:00
parent ae2a8929d8
commit 48b809e6e5
4 changed files with 58 additions and 0 deletions
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20
lib/Target/R600/AMDGPUInstructions.td
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@ -261,6 +261,26 @@ class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
(vt rc:$addr)
>;
// BFI_INT patterns
multiclass BFIPatterns <Instruction BFI_INT> {
// Definition from ISA doc:
// (y & x) | (z & ~x)
def : Pat <
(or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
(BFI_INT $x, $y, $z)
>;
// SHA-256 Ch function
// z ^ (x & (y ^ z))
def : Pat <
(xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
(BFI_INT $x, $y, $z)
>;
}
include "R600Instructions.td"
include "SIInstrInfo.td"

3
lib/Target/R600/R600Instructions.td
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@ -1570,6 +1570,9 @@ let Predicates = [isEGorCayman] in {
VecALU
>;
def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", []>;
defm : BFIPatterns <BFI_INT_eg>;
def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
[(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
R600_Reg32:$src2))],

1
lib/Target/R600/SIInstructions.td
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@ -948,6 +948,7 @@ def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
defm : BFIPatterns <V_BFI_B32>;
def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>;
def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>;
//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;

34
test/CodeGen/R600/bfi_int.ll Normal file
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@ -0,0 +1,34 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
; BFI_INT Definition pattern from ISA docs
; (y & x) | (z & ~x)
;
; R600-CHECK: @bfi_def
; R600-CHECK: BFI_INT
; SI-CHECK: @bfi_def
; SI-CHECK: V_BFI_B32
define void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
entry:
%0 = xor i32 %x, -1
%1 = and i32 %z, %0
%2 = and i32 %y, %x
%3 = or i32 %1, %2
store i32 %3, i32 addrspace(1)* %out
ret void
}
; SHA-256 Ch function
; z ^ (x & (y ^ z))
; R600-CHECK: @bfi_sha256_ch
; R600-CHECK: BFI_INT
; SI-CHECK: @bfi_sha256_ch
; SI-CHECK: V_BFI_B32
define void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
entry:
%0 = xor i32 %y, %z
%1 = and i32 %x, %0
%2 = xor i32 %z, %1
store i32 %2, i32 addrspace(1)* %out
ret void
}