diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index 53daa16aa93..ba733689daf 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -71,9 +71,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
                                            CodeModel::Model CM,
                                            CodeGenOpt::Level OL)
   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
-    DL("e-p:32:32:32-"
-                "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
-                "f64:64:64-f32:32:32-a:0-n32") ,
+    DL("e-p:32:32:32-i64:64:64-i1:32:32-a:0-n32") ,
     Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
     TSInfo(*this),
     FrameLowering(Subtarget),
diff --git a/lib/Target/MSP430/MSP430TargetMachine.cpp b/lib/Target/MSP430/MSP430TargetMachine.cpp
index 6710a097075..b27486d21ef 100644
--- a/lib/Target/MSP430/MSP430TargetMachine.cpp
+++ b/lib/Target/MSP430/MSP430TargetMachine.cpp
@@ -34,7 +34,7 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T,
   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
     Subtarget(TT, CPU, FS),
     // FIXME: Check DataLayout string.
-    DL("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
+    DL("e-p:16:16:16-i32:16:32-n8:16"),
     InstrInfo(*this), TLInfo(*this), TSInfo(*this),
     FrameLowering(Subtarget) {
   initAsmInfo();
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 43d6b1cfbc7..561b5e60bee 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -35,8 +35,6 @@ extern "C" void LLVMInitializePowerPCTarget() {
 
 /// Return the datalayout string of a subtarget.
 static std::string getDataLayoutString(const PPCSubtarget &ST) {
-  const Triple &T = ST.getTargetTriple();
-
   // PPC is big endian.
   std::string Ret = "E";
 
@@ -48,19 +46,11 @@ static std::string getDataLayoutString(const PPCSubtarget &ST) {
 
   // Note, the alignment values for f64 and i64 on ppc64 in Darwin
   // documentation are wrong; these are correct (i.e. "what gcc does").
-  Ret += "-f64:64:64-i64:64:64";
+  Ret += "-i64:64:64";
 
   // Set support for 128 floats depending on the ABI.
-  if (ST.isPPC64() && ST.isSVR4ABI()) {
-    if (T.getOS() != llvm::Triple::FreeBSD)
-      Ret += "-f128:128:128";
-  } else {
+  if (!ST.isPPC64() || !ST.isSVR4ABI())
     Ret += "-f128:64:128";
-  }
-
-  // Some ABIs support 128 bit vectors.
-  if (ST.isPPC64() && ST.isSVR4ABI())
-    Ret += "-v128:128:128";
 
   // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
   if (ST.isPPC64())
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 654b6255000..36d2f6f778d 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -33,13 +33,13 @@ static std::string computeDataLayout(const SparcSubtarget &ST) {
   else
     Ret += "-p:32:32:32";
 
-  // Alignments for 64 bit integers and doubles.
-  Ret += "-i64:64:64-f64:64:64";
+  // Alignments for 64 bit integers.
+  Ret += "-i64:64:64";
 
   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
   if (ST.is64Bit())
-    Ret += "-f128:128:128-n32:64";
+    Ret += "-n32:64";
   else
     Ret += "-f128:64:64-n32";
 
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 4d55b21f87b..274808839cd 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -47,9 +47,9 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
 
   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
   if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
-    Ret += "-f64:64:64-i64:64:64";
+    Ret += "-i64:64:64";
   else
-    Ret += "-f64:32:64-i64:32:64";
+    Ret += "-f64:32:64";
 
   // Some ABIs align long double to 128 bits, others to 32.
   if (ST.is64Bit() || ST.isTargetDarwin())
@@ -57,9 +57,6 @@ static std::string computeDataLayout(const X86Subtarget &ST) {
   else
     Ret += "-f80:32:32";
 
-  // 128 bit floats (?) are aligned to 128 bits.
-  Ret += "-f128:128:128";
-
   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
   if (ST.is64Bit())
     Ret += "-n8:16:32:64";
diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp
index 08fe55d2ae3..834d0a52fd3 100644
--- a/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -27,8 +27,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
                                        CodeGenOpt::Level OL)
   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
     Subtarget(TT, CPU, FS),
-    DL("e-p:32:32:32-a:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
-               "i16:16:32-i32:32:32-i64:32:32-n32"),
+    DL("e-p:32:32:32-a:0:32-f64:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32:32-n32"),
     InstrInfo(),
     FrameLowering(Subtarget),
     TLInfo(*this),