mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-24 08:33:39 +00:00
Nehalem unaligned memory access is fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100089 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
61336ae001
commit
48c58bb861
@ -59,6 +59,9 @@ def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
|
||||
[FeatureCMOV]>;
|
||||
def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
|
||||
"Bit testing of memory is slow">;
|
||||
def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
|
||||
"IsUAMemFast", "true",
|
||||
"Fast unaligned memory access">;
|
||||
def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
|
||||
"Support SSE 4a instructions">;
|
||||
|
||||
@ -98,8 +101,10 @@ def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
|
||||
def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
|
||||
def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
|
||||
def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
|
||||
def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
|
||||
def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
|
||||
def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
|
||||
FeatureFastUAMem]>;
|
||||
def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem,
|
||||
FeatureFastUAMem]>;
|
||||
// Sandy Bridge does not have FMA
|
||||
def : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>;
|
||||
|
||||
|
@ -266,6 +266,9 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
|
||||
unsigned Model = 0;
|
||||
DetectFamilyModel(EAX, Family, Model);
|
||||
IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
|
||||
// If it's Nehalem, unaligned memory access is fast.
|
||||
if (Family == 15 && Model == 26)
|
||||
IsUAMemFast = true;
|
||||
|
||||
GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
|
||||
HasX86_64 = (EDX >> 29) & 0x1;
|
||||
@ -286,6 +289,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
|
||||
, HasFMA3(false)
|
||||
, HasFMA4(false)
|
||||
, IsBTMemSlow(false)
|
||||
, IsUAMemFast(false)
|
||||
, HasVectorUAMem(false)
|
||||
, DarwinVers(0)
|
||||
, stackAlignment(8)
|
||||
|
@ -78,6 +78,9 @@ protected:
|
||||
/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
|
||||
bool IsBTMemSlow;
|
||||
|
||||
/// IsUAMemFast - True if unaligned memory access is fast.
|
||||
bool IsUAMemFast;
|
||||
|
||||
/// HasVectorUAMem - True if SIMD operations can have unaligned memory
|
||||
/// operands. This may require setting a feature bit in the
|
||||
/// processor.
|
||||
@ -148,6 +151,7 @@ public:
|
||||
bool hasFMA3() const { return HasFMA3; }
|
||||
bool hasFMA4() const { return HasFMA4; }
|
||||
bool isBTMemSlow() const { return IsBTMemSlow; }
|
||||
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
|
||||
bool hasVectorUAMem() const { return HasVectorUAMem; }
|
||||
|
||||
bool isTargetDarwin() const { return TargetType == isDarwin; }
|
||||
|
Loading…
x
Reference in New Issue
Block a user