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refactor some code into X86DAGToDAGISel::MatchWrapper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68915 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -162,6 +162,7 @@ namespace {
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bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
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bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
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bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
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bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
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unsigned Depth = 0);
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bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
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@ -782,6 +783,53 @@ bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
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return true;
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}
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bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
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bool is64Bit = Subtarget->is64Bit();
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DOUT << "Wrapper: 64bit " << is64Bit;
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DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
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// Under X86-64 non-small code model, GV (and friends) are 64-bits.
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// Also, base and index reg must be 0 in order to use rip as base.
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if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
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AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
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return true;
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if (AM.hasSymbolicDisplacement())
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return true;
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// If value is available in a register both base and index components have
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// been picked, we can't fit the result available in the register in the
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// addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
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SDValue N0 = N.getOperand(0);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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uint64_t Offset = G->getOffset();
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if (!is64Bit || isInt32(AM.Disp + Offset)) {
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GlobalValue *GV = G->getGlobal();
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AM.GV = GV;
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AM.Disp += Offset;
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AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
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return false;
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}
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
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uint64_t Offset = CP->getOffset();
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if (!is64Bit || isInt32(AM.Disp + Offset)) {
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += Offset;
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AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
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return false;
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}
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} else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
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AM.ES = S->getSymbol();
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AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
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return false;
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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AM.JT = J->getIndex();
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AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
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return false;
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}
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return true;
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}
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode.
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@ -822,51 +870,10 @@ bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
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return false;
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break;
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case X86ISD::Wrapper: {
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DOUT << "Wrapper: 64bit " << is64Bit;
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DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
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// Under X86-64 non-small code model, GV (and friends) are 64-bits.
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// Also, base and index reg must be 0 in order to use rip as base.
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if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
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AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
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break;
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if (AM.hasSymbolicDisplacement())
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break;
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// If value is available in a register both base and index components have
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// been picked, we can't fit the result available in the register in the
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// addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
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{
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SDValue N0 = N.getOperand(0);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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uint64_t Offset = G->getOffset();
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if (!is64Bit || isInt32(AM.Disp + Offset)) {
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GlobalValue *GV = G->getGlobal();
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AM.GV = GV;
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AM.Disp += Offset;
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AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
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return false;
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}
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
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uint64_t Offset = CP->getOffset();
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if (!is64Bit || isInt32(AM.Disp + Offset)) {
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += Offset;
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AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
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return false;
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}
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} else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
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AM.ES = S->getSymbol();
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AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
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return false;
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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AM.JT = J->getIndex();
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AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
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return false;
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}
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}
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case X86ISD::Wrapper:
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if (!MatchWrapper(N, AM))
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return false;
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break;
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}
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case ISD::LOAD:
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if (!MatchLoad(N, AM))
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