6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-20 14:29:27 +00:00
Code Issues Projects Releases Wiki Activity

padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27639 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-04-13 00:43:35 +00:00
parent a50a086341
commit 49ac1bf1c4
2 changed files with 106 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
include/llvm/IntrinsicsX86.td
View File

@ -250,6 +250,34 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
llvm_v2f64_ty], [IntrNoMem]>; llvm_v2f64_ty], [IntrNoMem]>;
} }
// Integer arithmetic ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_padds_b : GCCBuiltin<"__builtin_ia32_paddsb128">,
Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty,
llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_sse2_padds_w : GCCBuiltin<"__builtin_ia32_paddsw128">,
Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_sse2_paddus_b : GCCBuiltin<"__builtin_ia32_paddusb128">,
Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty,
llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_sse2_paddus_w : GCCBuiltin<"__builtin_ia32_paddusw128">,
Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_sse2_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb128">,
Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty,
llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_sse2_psubs_w : GCCBuiltin<"__builtin_ia32_psubsw128">,
Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
def int_x86_sse2_psubus_b : GCCBuiltin<"__builtin_ia32_psubusb128">,
Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty,
llvm_v16i8_ty], [IntrNoMem]>;
def int_x86_sse2_psubus_w : GCCBuiltin<"__builtin_ia32_psubusw128">,
Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
llvm_v8i16_ty], [IntrNoMem]>;
}
// Integer shift ops. // Integer shift ops.
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">, def int_x86_sse2_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi128">,

86
lib/Target/X86/X86InstrSSE.td
View File

@ -1283,23 +1283,59 @@ def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"paddq {$src2, $dst|$dst, $src2}", "paddq {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>; [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
} }
def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"paddb {$src2, $dst|$dst, $src2}", "paddb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v16i8 (add VR128:$src1, [(set VR128:$dst, (v16i8 (add VR128:$src1,
(load addr:$src2))))]>; (load addr:$src2))))]>;
def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"paddw {$src2, $dst|$dst, $src2}", "paddw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v8i16 (add VR128:$src1, [(set VR128:$dst, (v8i16 (add VR128:$src1,
(load addr:$src2))))]>; (load addr:$src2))))]>;
def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"paddd {$src2, $dst|$dst, $src2}", "paddd {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v4i32 (add VR128:$src1, [(set VR128:$dst, (v4i32 (add VR128:$src1,
(load addr:$src2))))]>; (load addr:$src2))))]>;
def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"paddd {$src2, $dst|$dst, $src2}", "paddd {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v2i64 (add VR128:$src1, [(set VR128:$dst, (v2i64 (add VR128:$src1,
(load addr:$src2))))]>; (load addr:$src2))))]>;
let isCommutable = 1 in {
def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"paddsb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
VR128:$src2))]>;
def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"paddsw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
VR128:$src2))]>;
def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"paddusb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
VR128:$src2))]>;
def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"paddusw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
VR128:$src2))]>;
}
def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"paddsb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
(bc_v16i8 (loadv2i64 addr:$src2))))]>;
def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"paddsw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
(bc_v8i16 (loadv2i64 addr:$src2))))]>;
def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"paddusb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
(bc_v16i8 (loadv2i64 addr:$src2))))]>;
def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"paddusw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
(bc_v8i16 (loadv2i64 addr:$src2))))]>;
def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"psubb {$src2, $dst|$dst, $src2}", "psubb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>; [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
@ -1313,22 +1349,56 @@ def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"psubq {$src2, $dst|$dst, $src2}", "psubq {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>; [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"psubb {$src2, $dst|$dst, $src2}", "psubb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v16i8 (sub VR128:$src1, [(set VR128:$dst, (v16i8 (sub VR128:$src1,
(load addr:$src2))))]>; (load addr:$src2))))]>;
def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"psubw {$src2, $dst|$dst, $src2}", "psubw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v8i16 (sub VR128:$src1, [(set VR128:$dst, (v8i16 (sub VR128:$src1,
(load addr:$src2))))]>; (load addr:$src2))))]>;
def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"psubd {$src2, $dst|$dst, $src2}", "psubd {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v4i32 (sub VR128:$src1, [(set VR128:$dst, (v4i32 (sub VR128:$src1,
(load addr:$src2))))]>; (load addr:$src2))))]>;
def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"psubd {$src2, $dst|$dst, $src2}", "psubd {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v2i64 (sub VR128:$src1, [(set VR128:$dst, (v2i64 (sub VR128:$src1,
(load addr:$src2))))]>; (load addr:$src2))))]>;
def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"psubsb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
VR128:$src2))]>;
def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"psubsw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
VR128:$src2))]>;
def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"psubusb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
VR128:$src2))]>;
def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
"psubusw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
VR128:$src2))]>;
def PSUBSBrm : PDI<0xE8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"psubsb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
(bc_v16i8 (loadv2i64 addr:$src2))))]>;
def PSUBSWrm : PDI<0xE9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"psubsw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
(bc_v8i16 (loadv2i64 addr:$src2))))]>;
def PSUBUSBrm : PDI<0xD8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"psubusb {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
(bc_v16i8 (loadv2i64 addr:$src2))))]>;
def PSUBUSWrm : PDI<0xD9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
"psubusw {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
(bc_v8i16 (loadv2i64 addr:$src2))))]>;
} }
let isTwoAddress = 1 in { let isTwoAddress = 1 in {