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Use TRI::printReg instead of AbstractRegisterDescription when printing

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LiveIntervalUnions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-12-14 18:53:47 +00:00
parent 414e5023f8
commit 4a84cce3ed
3 changed files with 13 additions and 34 deletions
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11
lib/CodeGen/RegAllocBasic.cpp
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@@ -60,14 +60,6 @@ VerifyRegAlloc("verify-regalloc",
const char *RegAllocBase::TimerGroupName = "Register Allocation";
namespace {
class PhysicalRegisterDescription : public AbstractRegisterDescription {
const TargetRegisterInfo *TRI;
public:
PhysicalRegisterDescription(const TargetRegisterInfo *T): TRI(T) {}
virtual const char *getName(unsigned Reg) const { return TRI->getName(Reg); }
};
/// RABasic provides a minimal implementation of the basic register allocation
/// algorithm. It prioritizes live virtual registers by spill weight and spills
/// whenever a register is unavailable. This is not practical in production but
@@ -165,8 +157,7 @@ void RegAllocBase::verify() {
// Verify disjoint unions.
for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
DEBUG(PhysicalRegisterDescription PRD(TRI);
PhysReg2LiveUnion[PhysReg].dump(&PRD));
DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
PhysReg2LiveUnion[PhysReg].verify(VRegs);
// Union + intersection test could be done efficiently in one pass, but