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R600/SI: Add FMA pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188135 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1007,8 +1007,12 @@ def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
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def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
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def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
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defm : BFIPatterns <V_BFI_B32>;
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def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>;
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def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>;
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def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
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[(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
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>;
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def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
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[(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
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>;
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//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
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def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
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def : ROTRPattern <V_ALIGNBIT_B32>;
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31
test/CodeGen/R600/fma.ll
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31
test/CodeGen/R600/fma.ll
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@ -0,0 +1,31 @@
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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; CHECK: @fma_f32
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; CHECK: V_FMA_F32 {{VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
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define void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2, float addrspace(1)* %in3) {
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%r0 = load float addrspace(1)* %in1
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%r1 = load float addrspace(1)* %in2
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%r2 = load float addrspace(1)* %in3
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%r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %out
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ret void
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}
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declare float @llvm.fma.f32(float, float, float)
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; CHECK: @fma_f64
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; CHECK: V_FMA_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
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define void @fma_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2, double addrspace(1)* %in3) {
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%r0 = load double addrspace(1)* %in1
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%r1 = load double addrspace(1)* %in2
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%r2 = load double addrspace(1)* %in3
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%r3 = tail call double @llvm.fma.f64(double %r0, double %r1, double %r2)
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store double %r3, double addrspace(1)* %out
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ret void
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}
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declare double @llvm.fma.f64(double, double, double)
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