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R600/SI: Remove assert

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Since read2 / write2 are emitted for 4-byte aligned 8-byte
accesses, these are seen by the scheduler.

The DAG scheduler is semi-deprecated, so just
ignore these for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217969 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-09-17 17:48:32 +00:00
parent 3143460f91
commit 4ad9b914ee
1 changed files with 7 additions and 6 deletions
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13
lib/Target/R600/SIInstrInfo.cpp
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@ -89,12 +89,6 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
if (isDS(Opc0) && isDS(Opc1)) {
assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
// TODO: Also shouldn't see read2st
assert(Opc0 != AMDGPU::DS_READ2_B32 &&
Opc0 != AMDGPU::DS_READ2_B64 &&
Opc1 != AMDGPU::DS_READ2_B32 &&
Opc1 != AMDGPU::DS_READ2_B64);
// Check base reg.
if (Load0->getOperand(1) != Load1->getOperand(1))
return false;
@ -103,6 +97,13 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
if (findChainOperand(Load0) != findChainOperand(Load1))
return false;
// Skip read2 / write2 variants for simplicity.
// TODO: We should report true if the used offsets are adjacent (excluded
// st64 versions).
if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
return false;
Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
return true;