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https://github.com/c64scene-ar/llvm-6502.git
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NEON VST3(single element from one lane) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
392ad6d8aa
commit
4adb182342
@ -6085,6 +6085,56 @@ def VLD3qWB_register_Asm_32 :
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(ins VecListThreeQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VST3 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
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(ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
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(ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
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(ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
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(ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
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(ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNdWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
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(ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNdWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
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(ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNdWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
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(ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNqWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
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(ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNqWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
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(ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
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def VST3LNdWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
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(ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST3LNdWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
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(ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST3LNdWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
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(ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST3LNqWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
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(ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VST3LNqWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
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(ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VST3 multiple structurepseudo-instructions. These need special handling for
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// the vector operands that the normal instructions don't yet model.
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// FIXME: Remove these when the register classes and instructions are updated.
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@ -5254,6 +5254,53 @@ static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
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Spacing = 2;
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return ARM::VST2LNq32;
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// VST3LN
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case ARM::VST3LNdWB_fixed_Asm_8:
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Spacing = 1;
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return ARM::VST3LNd8_UPD;
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case ARM::VST3LNdWB_fixed_Asm_16:
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Spacing = 1;
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return ARM::VST3LNd16_UPD;
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case ARM::VST3LNdWB_fixed_Asm_32:
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Spacing = 1;
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return ARM::VST3LNd32_UPD;
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case ARM::VST3LNqWB_fixed_Asm_16:
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Spacing = 1;
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return ARM::VST3LNq16_UPD;
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case ARM::VST3LNqWB_fixed_Asm_32:
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Spacing = 2;
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return ARM::VST3LNq32_UPD;
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case ARM::VST3LNdWB_register_Asm_8:
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Spacing = 1;
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return ARM::VST3LNd8_UPD;
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case ARM::VST3LNdWB_register_Asm_16:
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Spacing = 1;
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return ARM::VST3LNd16_UPD;
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case ARM::VST3LNdWB_register_Asm_32:
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Spacing = 1;
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return ARM::VST3LNd32_UPD;
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case ARM::VST3LNqWB_register_Asm_16:
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Spacing = 2;
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return ARM::VST3LNq16_UPD;
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case ARM::VST3LNqWB_register_Asm_32:
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Spacing = 2;
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return ARM::VST3LNq32_UPD;
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case ARM::VST3LNdAsm_8:
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Spacing = 1;
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return ARM::VST3LNd8;
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case ARM::VST3LNdAsm_16:
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Spacing = 1;
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return ARM::VST3LNd16;
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case ARM::VST3LNdAsm_32:
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Spacing = 1;
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return ARM::VST3LNd32;
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case ARM::VST3LNqAsm_16:
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Spacing = 2;
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return ARM::VST3LNq16;
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case ARM::VST3LNqAsm_32:
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Spacing = 2;
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return ARM::VST3LNq32;
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// VST3
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case ARM::VST3dWB_fixed_Asm_8:
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Spacing = 1;
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@ -5560,6 +5607,33 @@ processInstruction(MCInst &Inst,
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Inst = TmpInst;
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return true;
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}
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case ARM::VST3LNdWB_register_Asm_8:
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case ARM::VST3LNdWB_register_Asm_16:
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case ARM::VST3LNdWB_register_Asm_32:
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case ARM::VST3LNqWB_register_Asm_16:
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case ARM::VST3LNqWB_register_Asm_32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(4)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(5)); // CondCode
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TmpInst.addOperand(Inst.getOperand(6));
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Inst = TmpInst;
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return true;
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}
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case ARM::VST1LNdWB_fixed_Asm_8:
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case ARM::VST1LNdWB_fixed_Asm_16:
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case ARM::VST1LNdWB_fixed_Asm_32: {
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@ -5603,6 +5677,33 @@ processInstruction(MCInst &Inst,
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Inst = TmpInst;
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return true;
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}
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case ARM::VST3LNdWB_fixed_Asm_8:
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case ARM::VST3LNdWB_fixed_Asm_16:
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case ARM::VST3LNdWB_fixed_Asm_32:
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case ARM::VST3LNqWB_fixed_Asm_16:
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case ARM::VST3LNqWB_fixed_Asm_32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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case ARM::VST1LNdAsm_8:
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case ARM::VST1LNdAsm_16:
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case ARM::VST1LNdAsm_32: {
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@ -5642,6 +5743,31 @@ processInstruction(MCInst &Inst,
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Inst = TmpInst;
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return true;
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}
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case ARM::VST3LNdAsm_8:
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case ARM::VST3LNdAsm_16:
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case ARM::VST3LNdAsm_32:
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case ARM::VST3LNqAsm_16:
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case ARM::VST3LNqAsm_32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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unsigned Spacing;
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TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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// Handle NEON VLD complex aliases.
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case ARM::VLD1LNdWB_register_Asm_8:
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case ARM::VLD1LNdWB_register_Asm_16:
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@ -153,6 +153,41 @@
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@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
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vst3.8 {d16[1], d17[1], d18[1]}, [r1]
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vst3.16 {d6[1], d7[1], d8[1]}, [r2]
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vst3.32 {d1[1], d2[1], d3[1]}, [r3]
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vst3.u16 {d27[1], d29[1], d31[1]}, [r4]
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vst3.i32 {d6[1], d8[1], d10[1]}, [r5]
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vst3.i8 {d12[1], d13[1], d14[1]}, [r6], r1
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vst3.i16 {d11[1], d12[1], d13[1]}, [r7], r2
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vst3.u32 {d2[1], d3[1], d4[1]}, [r8], r3
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vst3.u16 {d14[1], d16[1], d18[1]}, [r9], r4
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vst3.i32 {d16[1], d18[1], d20[1]}, [r10], r5
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vst3.p8 {d6[1], d7[1], d8[1]}, [r8]!
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vst3.16 {d9[1], d10[1], d11[1]}, [r7]!
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vst3.f32 {d1[1], d2[1], d3[1]}, [r6]!
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vst3.p16 {d20[1], d22[1], d24[1]}, [r5]!
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vst3.32 {d5[1], d7[1], d9[1]}, [r4]!
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@ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r1] @ encoding: [0x2f,0x02,0xc1,0xf4]
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@ CHECK: vst3.16 {d6[1], d7[1], d8[1]}, [r2] @ encoding: [0x4f,0x66,0x82,0xf4]
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@ CHECK: vst3.32 {d1[1], d2[1], d3[1]}, [r3] @ encoding: [0x8f,0x1a,0x83,0xf4]
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@ CHECK: vst3.16 {d27[1], d29[1], d31[1]}, [r4] @ encoding: [0x6f,0xb6,0xc4,0xf4]
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@ CHECK: vst3.32 {d6[1], d8[1], d10[1]}, [r5] @ encoding: [0xcf,0x6a,0x85,0xf4]
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@ CHECK: vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1 @ encoding: [0x21,0xc2,0x86,0xf4]
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@ CHECK: vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2 @ encoding: [0x42,0xb6,0x87,0xf4]
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@ CHECK: vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3 @ encoding: [0x83,0x2a,0x88,0xf4]
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@ CHECK: vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4 @ encoding: [0x64,0xe6,0x89,0xf4]
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@ CHECK: vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5 @ encoding: [0xc5,0x0a,0xca,0xf4]
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@ CHECK: vst3.8 {d6[1], d7[1], d8[1]}, [r8]! @ encoding: [0x2d,0x62,0x88,0xf4]
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@ CHECK: vst3.16 {d9[1], d10[1], d11[1]}, [r7]! @ encoding: [0x4d,0x96,0x87,0xf4]
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@ CHECK: vst3.32 {d1[1], d2[1], d3[1]}, [r6]! @ encoding: [0x8d,0x1a,0x86,0xf4]
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@ CHECK: vst3.16 {d20[1], d21[1], d22[1]}, [r5]! @ encoding: [0x6d,0x46,0xc5,0xf4]
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@ CHECK: vst3.32 {d5[1], d7[1], d9[1]}, [r4]! @ encoding: [0xcd,0x5a,0x84,0xf4]
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@ vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
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@ vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
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@ vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
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