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Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
2012-03-01 18:16:35 +00:00
parent b5372769eb
commit 4b1212b4bf
3 changed files with 10 additions and 16 deletions
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10
include/llvm/MC/MCRegisterInfo.h
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@@ -248,6 +248,16 @@ public:
return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1); return *(SubRegIndices + (Reg - 1) * NumSubRegIndices + Idx - 1);
} }
/// getSubRegIndex - For a given register pair, return the sub-register index
/// if the second register is a sub-register of the first. Return zero
/// otherwise.
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {
for (unsigned I = 1; I <= NumSubRegIndices; ++I)
if (getSubReg(RegNo, I) == SubRegNo)
return I;
return 0;
}
/// getSuperRegisters - Return the list of registers that are super-registers /// getSuperRegisters - Return the list of registers that are super-registers
/// of the specified register, or a null list of there are none. The list /// of the specified register, or a null list of there are none. The list
/// returned is zero terminated and sorted according to super-sub register /// returned is zero terminated and sorted according to super-sub register

5
include/llvm/Target/TargetRegisterInfo.h
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@@ -383,11 +383,6 @@ public:
/// used by register scavenger to determine what registers are free. /// used by register scavenger to determine what registers are free.
virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
/// getSubRegIndex - For a given register pair, return the sub-register index
/// if the second register is a sub-register of the first. Return zero
/// otherwise.
virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
/// getMatchingSuperReg - Return a super-register of the specified register /// getMatchingSuperReg - Return a super-register of the specified register
/// Reg so its sub-register of index SubIdx is Reg. /// Reg so its sub-register of index SubIdx is Reg.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,

11
utils/TableGen/RegisterInfoEmitter.cpp
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@@ -486,7 +486,6 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
<< "(unsigned RA, unsigned D = 0, unsigned E = 0);\n" << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
<< " virtual bool needsStackRealignment(const MachineFunction &) const\n" << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
<< " { return false; }\n" << " { return false; }\n"
<< " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
<< " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
<< " const TargetRegisterClass *" << " const TargetRegisterClass *"
"getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n" "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
@@ -766,16 +765,6 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
std::string ClassName = Target.getName() + "GenRegisterInfo"; std::string ClassName = Target.getName() + "GenRegisterInfo";
OS << "unsigned " << ClassName
<< "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n";
if (SubRegIndices.size()) {
OS << " for (unsigned I = 1; I <= " << SubRegIndices.size() << "; ++I)\n"
<< " if (getSubReg(RegNo, I) == SubRegNo)\n"
<< " return I;\n";
}
OS << " return 0;\n";
OS << "}\n\n";
// Emit composeSubRegIndices // Emit composeSubRegIndices
OS << "unsigned " << ClassName OS << "unsigned " << ClassName
<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n" << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"