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Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, Ptr, etc.

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No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2012-07-11 11:02:16 +00:00
parent a67306d21f
commit 4b24bf8da3
1 changed files with 104 additions and 100 deletions
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204
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -642,9 +642,8 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
// probably means that we need to integrate dag combiner and legalizer // probably means that we need to integrate dag combiner and legalizer
// together. // together.
// We generally can't do this one for long doubles. // We generally can't do this one for long doubles.
SDValue Tmp1 = ST->getChain(); SDValue Chain = ST->getChain();
SDValue Tmp2 = ST->getBasePtr(); SDValue Ptr = ST->getBasePtr();
SDValue Tmp3;
unsigned Alignment = ST->getAlignment(); unsigned Alignment = ST->getAlignment();
bool isVolatile = ST->isVolatile(); bool isVolatile = ST->isVolatile();
bool isNonTemporal = ST->isNonTemporal(); bool isNonTemporal = ST->isNonTemporal();
@ -652,19 +651,19 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
if (CFP->getValueType(0) == MVT::f32 && if (CFP->getValueType(0) == MVT::f32 &&
TLI.isTypeLegal(MVT::i32)) { TLI.isTypeLegal(MVT::i32)) {
Tmp3 = DAG.getConstant(CFP->getValueAPF(). SDValue Con = DAG.getConstant(CFP->getValueAPF().
bitcastToAPInt().zextOrTrunc(32), bitcastToAPInt().zextOrTrunc(32),
MVT::i32); MVT::i32);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
isVolatile, isNonTemporal, Alignment); isVolatile, isNonTemporal, Alignment);
} }
if (CFP->getValueType(0) == MVT::f64) { if (CFP->getValueType(0) == MVT::f64) {
// If this target supports 64-bit registers, do a single 64-bit store. // If this target supports 64-bit registers, do a single 64-bit store.
if (TLI.isTypeLegal(MVT::i64)) { if (TLI.isTypeLegal(MVT::i64)) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
zextOrTrunc(64), MVT::i64); zextOrTrunc(64), MVT::i64);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
isVolatile, isNonTemporal, Alignment); isVolatile, isNonTemporal, Alignment);
} }
@ -677,11 +676,11 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi); if (TLI.isBigEndian()) std::swap(Lo, Hi);
Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile, Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
isNonTemporal, Alignment); isNonTemporal, Alignment);
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(4)); DAG.getIntPtrConstant(4));
Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, Hi = DAG.getStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(4), ST->getPointerInfo().getWithOffset(4),
isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
@ -694,8 +693,8 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) { void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
StoreSDNode *ST = cast<StoreSDNode>(Node); StoreSDNode *ST = cast<StoreSDNode>(Node);
SDValue Tmp1 = ST->getChain(); SDValue Chain = ST->getChain();
SDValue Tmp2 = ST->getBasePtr(); SDValue Ptr = ST->getBasePtr();
DebugLoc dl = Node->getDebugLoc(); DebugLoc dl = Node->getDebugLoc();
unsigned Alignment = ST->getAlignment(); unsigned Alignment = ST->getAlignment();
@ -709,8 +708,8 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
} }
{ {
SDValue Tmp3 = ST->getValue(); SDValue Value = ST->getValue();
EVT VT = Tmp3.getValueType(); EVT VT = Value.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) { switch (TLI.getOperationAction(ISD::STORE, VT)) {
default: llvm_unreachable("This action is not supported yet!"); default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal: case TargetLowering::Legal:
@ -724,17 +723,18 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
DAG, TLI, this); DAG, TLI, this);
} }
break; break;
case TargetLowering::Custom: case TargetLowering::Custom: {
Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
if (Tmp1.getNode()) if (Res.getNode())
ReplaceNode(SDValue(Node, 0), Tmp1); ReplaceNode(SDValue(Node, 0), Res);
break; return;
}
case TargetLowering::Promote: { case TargetLowering::Promote: {
assert(VT.isVector() && "Unknown legal promote case!"); assert(VT.isVector() && "Unknown legal promote case!");
Tmp3 = DAG.getNode(ISD::BITCAST, dl, Value = DAG.getNode(ISD::BITCAST, dl,
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); TLI.getTypeToPromoteTo(ISD::STORE, VT), Value);
SDValue Result = SDValue Result =
DAG.getStore(Tmp1, dl, Tmp3, Tmp2, DAG.getStore(Chain, dl, Value, Ptr,
ST->getPointerInfo(), isVolatile, ST->getPointerInfo(), isVolatile,
isNonTemporal, Alignment); isNonTemporal, Alignment);
ReplaceNode(SDValue(Node, 0), Result); ReplaceNode(SDValue(Node, 0), Result);
@ -744,7 +744,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
return; return;
} }
} else { } else {
SDValue Tmp3 = ST->getValue(); SDValue Value = ST->getValue();
EVT StVT = ST->getMemoryVT(); EVT StVT = ST->getMemoryVT();
unsigned StWidth = StVT.getSizeInBits(); unsigned StWidth = StVT.getSizeInBits();
@ -755,9 +755,9 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
EVT NVT = EVT::getIntegerVT(*DAG.getContext(), EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
StVT.getStoreSizeInBits()); StVT.getStoreSizeInBits());
Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); Value = DAG.getZeroExtendInReg(Value, dl, StVT);
SDValue Result = SDValue Result =
DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
NVT, isVolatile, isNonTemporal, Alignment); NVT, isVolatile, isNonTemporal, Alignment);
ReplaceNode(SDValue(Node, 0), Result); ReplaceNode(SDValue(Node, 0), Result);
} else if (StWidth & (StWidth - 1)) { } else if (StWidth & (StWidth - 1)) {
@ -777,18 +777,18 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
if (TLI.isLittleEndian()) { if (TLI.isLittleEndian()) {
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
// Store the bottom RoundWidth bits. // Store the bottom RoundWidth bits.
Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
RoundVT, RoundVT,
isVolatile, isNonTemporal, Alignment); isVolatile, isNonTemporal, Alignment);
// Store the remaining ExtraWidth bits. // Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8; IncrementSize = RoundWidth / 8;
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize)); DAG.getIntPtrConstant(IncrementSize));
Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
DAG.getConstant(RoundWidth, DAG.getConstant(RoundWidth,
TLI.getShiftAmountTy(Tmp3.getValueType()))); TLI.getShiftAmountTy(Value.getValueType())));
Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize), ST->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, isVolatile, isNonTemporal, ExtraVT, isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize)); MinAlign(Alignment, IncrementSize));
@ -796,17 +796,17 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// Big endian - avoid unaligned stores. // Big endian - avoid unaligned stores.
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
// Store the top RoundWidth bits. // Store the top RoundWidth bits.
Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
DAG.getConstant(ExtraWidth, DAG.getConstant(ExtraWidth,
TLI.getShiftAmountTy(Tmp3.getValueType()))); TLI.getShiftAmountTy(Value.getValueType())));
Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(), Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
RoundVT, isVolatile, isNonTemporal, Alignment); RoundVT, isVolatile, isNonTemporal, Alignment);
// Store the remaining ExtraWidth bits. // Store the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8; IncrementSize = RoundWidth / 8;
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize)); DAG.getIntPtrConstant(IncrementSize));
Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
ST->getPointerInfo().getWithOffset(IncrementSize), ST->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, isVolatile, isNonTemporal, ExtraVT, isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize)); MinAlign(Alignment, IncrementSize));
@ -828,20 +828,22 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this); ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
} }
break; break;
case TargetLowering::Custom: case TargetLowering::Custom: {
Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
if (Tmp1.getNode()) if (Res.getNode())
ReplaceNode(SDValue(Node, 0), Tmp1); ReplaceNode(SDValue(Node, 0), Res);
break; return;
}
case TargetLowering::Expand: case TargetLowering::Expand:
assert(!StVT.isVector() && assert(!StVT.isVector() &&
"Vector Stores are handled in LegalizeVectorOps"); "Vector Stores are handled in LegalizeVectorOps");
// TRUNCSTORE:i16 i32 -> STORE i16 // TRUNCSTORE:i16 i32 -> STORE i16
assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!"); assert(TLI.isTypeLegal(StVT) &&
Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); "Do not know how to expand this store!");
Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
SDValue Result = SDValue Result =
DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
isVolatile, isNonTemporal, Alignment); isVolatile, isNonTemporal, Alignment);
ReplaceNode(SDValue(Node, 0), Result); ReplaceNode(SDValue(Node, 0), Result);
break; break;
@ -852,15 +854,16 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) { void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
LoadSDNode *LD = cast<LoadSDNode>(Node); LoadSDNode *LD = cast<LoadSDNode>(Node);
SDValue Tmp1 = LD->getChain(); // Legalize the chain. SDValue Chain = LD->getChain(); // The chain.
SDValue Tmp2 = LD->getBasePtr(); // Legalize the base pointer. SDValue Ptr = LD->getBasePtr(); // The base pointer.
SDValue Value; // The value returned by the load op.
DebugLoc dl = Node->getDebugLoc(); DebugLoc dl = Node->getDebugLoc();
ISD::LoadExtType ExtType = LD->getExtensionType(); ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD) { if (ExtType == ISD::NON_EXTLOAD) {
EVT VT = Node->getValueType(0); EVT VT = Node->getValueType(0);
SDValue Tmp3 = SDValue(Node, 0); SDValue RVal = SDValue(Node, 0);
SDValue Tmp4 = SDValue(Node, 1); SDValue RChain = SDValue(Node, 1);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) { switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: llvm_unreachable("This action is not supported yet!"); default: llvm_unreachable("This action is not supported yet!");
@ -869,38 +872,40 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// expand it. // expand it.
if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); unsigned ABIAlignment =
TLI.getTargetData()->getABITypeAlignment(Ty);
if (LD->getAlignment() < ABIAlignment){ if (LD->getAlignment() < ABIAlignment){
ExpandUnalignedLoad(cast<LoadSDNode>(Node), ExpandUnalignedLoad(cast<LoadSDNode>(Node),
DAG, TLI, Tmp3, Tmp4); DAG, TLI, RVal, RChain);
} }
} }
break; break;
case TargetLowering::Custom: case TargetLowering::Custom: {
Tmp1 = TLI.LowerOperation(Tmp3, DAG); SDValue Res = TLI.LowerOperation(RVal, DAG);
if (Tmp1.getNode()) { if (Res.getNode()) {
Tmp3 = Tmp1; RVal = Res;
Tmp4 = Tmp1.getValue(1); RChain = Res.getValue(1);
} }
break; break;
}
case TargetLowering::Promote: { case TargetLowering::Promote: {
// Only promote a load of vector type to another. // Only promote a load of vector type to another.
assert(VT.isVector() && "Cannot promote this load!"); assert(VT.isVector() && "Cannot promote this load!");
// Change base type to a different vector type. // Change base type to a different vector type.
EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(),
LD->isVolatile(), LD->isNonTemporal(), LD->isVolatile(), LD->isNonTemporal(),
LD->isInvariant(), LD->getAlignment()); LD->isInvariant(), LD->getAlignment());
Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1); RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
Tmp4 = Tmp1.getValue(1); RChain = Res.getValue(1);
break; break;
} }
} }
if (Tmp4.getNode() != Node) { if (RChain.getNode() != Node) {
assert(Tmp3.getNode() != Node && "Load must be completely replaced"); assert(RVal.getNode() != Node && "Load must be completely replaced");
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3); DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4); DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
ReplacedNode(Node); ReplacedNode(Node);
} }
return; return;
@ -936,7 +941,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
SDValue Result = SDValue Result =
DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
Tmp1, Tmp2, LD->getPointerInfo(), Chain, Ptr, LD->getPointerInfo(),
NVT, isVolatile, isNonTemporal, Alignment); NVT, isVolatile, isNonTemporal, Alignment);
Ch = Result.getValue(1); // The chain. Ch = Result.getValue(1); // The chain.
@ -952,8 +957,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
Result.getValueType(), Result, Result.getValueType(), Result,
DAG.getValueType(SrcVT)); DAG.getValueType(SrcVT));
Tmp1 = Result; Value = Result;
Tmp2 = Ch; Chain = Ch;
} else if (SrcWidth & (SrcWidth - 1)) { } else if (SrcWidth & (SrcWidth - 1)) {
// If not loading a power-of-2 number of bits, expand as two loads. // If not loading a power-of-2 number of bits, expand as two loads.
assert(!SrcVT.isVector() && "Unsupported extload!"); assert(!SrcVT.isVector() && "Unsupported extload!");
@ -972,15 +977,15 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
// Load the bottom RoundWidth bits. // Load the bottom RoundWidth bits.
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
Tmp1, Tmp2, Chain, Ptr,
LD->getPointerInfo(), RoundVT, isVolatile, LD->getPointerInfo(), RoundVT, isVolatile,
isNonTemporal, Alignment); isNonTemporal, Alignment);
// Load the remaining ExtraWidth bits. // Load the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8; IncrementSize = RoundWidth / 8;
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize)); DAG.getIntPtrConstant(IncrementSize));
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, isVolatile, isNonTemporal, ExtraVT, isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize)); MinAlign(Alignment, IncrementSize));
@ -996,21 +1001,21 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
TLI.getShiftAmountTy(Hi.getValueType()))); TLI.getShiftAmountTy(Hi.getValueType())));
// Join the hi and lo parts. // Join the hi and lo parts.
Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
} else { } else {
// Big endian - avoid unaligned loads. // Big endian - avoid unaligned loads.
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
// Load the top RoundWidth bits. // Load the top RoundWidth bits.
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo(), RoundVT, isVolatile, LD->getPointerInfo(), RoundVT, isVolatile,
isNonTemporal, Alignment); isNonTemporal, Alignment);
// Load the remaining ExtraWidth bits. // Load the remaining ExtraWidth bits.
IncrementSize = RoundWidth / 8; IncrementSize = RoundWidth / 8;
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
DAG.getIntPtrConstant(IncrementSize)); DAG.getIntPtrConstant(IncrementSize));
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
dl, Node->getValueType(0), Tmp1, Tmp2, dl, Node->getValueType(0), Chain, Ptr,
LD->getPointerInfo().getWithOffset(IncrementSize), LD->getPointerInfo().getWithOffset(IncrementSize),
ExtraVT, isVolatile, isNonTemporal, ExtraVT, isVolatile, isNonTemporal,
MinAlign(Alignment, IncrementSize)); MinAlign(Alignment, IncrementSize));
@ -1026,10 +1031,10 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
TLI.getShiftAmountTy(Hi.getValueType()))); TLI.getShiftAmountTy(Hi.getValueType())));
// Join the hi and lo parts. // Join the hi and lo parts.
Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
} }
Tmp2 = Ch; Chain = Ch;
} else { } else {
bool isCustom = false; bool isCustom = false;
switch (TLI.getLoadExtAction(ExtType, SrcVT)) { switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
@ -1037,15 +1042,15 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
case TargetLowering::Custom: case TargetLowering::Custom:
isCustom = true; isCustom = true;
// FALLTHROUGH // FALLTHROUGH
case TargetLowering::Legal: case TargetLowering::Legal: {
Tmp1 = SDValue(Node, 0); Value = SDValue(Node, 0);
Tmp2 = SDValue(Node, 1); Chain = SDValue(Node, 1);
if (isCustom) { if (isCustom) {
SDValue Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG); SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
if (Tmp3.getNode()) { if (Res.getNode()) {
Tmp1 = Tmp3; Value = Res;
Tmp2 = Tmp3.getValue(1); Chain = Res.getValue(1);
} }
} else { } else {
// If this is an unaligned load and the target doesn't support it, // If this is an unaligned load and the target doesn't support it,
@ -1057,14 +1062,15 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
TLI.getTargetData()->getABITypeAlignment(Ty); TLI.getTargetData()->getABITypeAlignment(Ty);
if (LD->getAlignment() < ABIAlignment){ if (LD->getAlignment() < ABIAlignment){
ExpandUnalignedLoad(cast<LoadSDNode>(Node), ExpandUnalignedLoad(cast<LoadSDNode>(Node),
DAG, TLI, Tmp1, Tmp2); DAG, TLI, Value, Chain);
} }
} }
} }
break; break;
}
case TargetLowering::Expand: case TargetLowering::Expand:
if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) { if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr,
LD->getPointerInfo(), LD->getPointerInfo(),
LD->isVolatile(), LD->isNonTemporal(), LD->isVolatile(), LD->isNonTemporal(),
LD->isInvariant(), LD->getAlignment()); LD->isInvariant(), LD->getAlignment());
@ -1078,8 +1084,8 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
default: llvm_unreachable("Unexpected extend load type!"); default: llvm_unreachable("Unexpected extend load type!");
} }
Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
Tmp2 = Load.getValue(1); Chain = Load.getValue(1);
break; break;
} }
@ -1095,7 +1101,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
// Turn the unsupported load into an EXTLOAD followed by an explicit // Turn the unsupported load into an EXTLOAD followed by an explicit
// zero/sign extend inreg. // zero/sign extend inreg.
SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
Tmp1, Tmp2, LD->getPointerInfo(), SrcVT, Chain, Ptr, LD->getPointerInfo(), SrcVT,
LD->isVolatile(), LD->isNonTemporal(), LD->isVolatile(), LD->isNonTemporal(),
LD->getAlignment()); LD->getAlignment());
SDValue ValRes; SDValue ValRes;
@ -1105,18 +1111,18 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
Result, DAG.getValueType(SrcVT)); Result, DAG.getValueType(SrcVT));
else else
ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
Tmp1 = ValRes; Value = ValRes;
Tmp2 = Result.getValue(1); Chain = Result.getValue(1);
break; break;
} }
} }
// Since loads produce two values, make sure to remember that we legalized // Since loads produce two values, make sure to remember that we legalized
// both of them. // both of them.
if (Tmp2.getNode() != Node) { if (Chain.getNode() != Node) {
assert(Tmp1.getNode() != Node && "Load must be completely replaced"); assert(Value.getNode() != Node && "Load must be completely replaced");
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1); DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2); DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
ReplacedNode(Node); ReplacedNode(Node);
} }
} }
@ -1139,8 +1145,6 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
Node->getOperand(i).getOpcode() == ISD::TargetConstant) && Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
"Unexpected illegal type!"); "Unexpected illegal type!");
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
// Figure out the correct action; the way to query this varies by opcode // Figure out the correct action; the way to query this varies by opcode
TargetLowering::LegalizeAction Action = TargetLowering::Legal; TargetLowering::LegalizeAction Action = TargetLowering::Legal;
bool SimpleFinishLegalizing = true; bool SimpleFinishLegalizing = true;
@ -1294,19 +1298,19 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
switch (Action) { switch (Action) {
case TargetLowering::Legal: case TargetLowering::Legal:
return; return;
case TargetLowering::Custom: case TargetLowering::Custom: {
// FIXME: The handling for custom lowering with multiple results is // FIXME: The handling for custom lowering with multiple results is
// a complete mess. // a complete mess.
Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
if (Tmp1.getNode()) { if (Res.getNode()) {
SmallVector<SDValue, 8> ResultVals; SmallVector<SDValue, 8> ResultVals;
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
if (e == 1) if (e == 1)
ResultVals.push_back(Tmp1); ResultVals.push_back(Res);
else else
ResultVals.push_back(Tmp1.getValue(i)); ResultVals.push_back(Res.getValue(i));
} }
if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) { if (Res.getNode() != Node || Res.getResNo() != 0) {
DAG.ReplaceAllUsesWith(Node, ResultVals.data()); DAG.ReplaceAllUsesWith(Node, ResultVals.data());
for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]); DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]);
@ -1314,7 +1318,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
} }
return; return;
} }
}
// FALL THROUGH // FALL THROUGH
case TargetLowering::Expand: case TargetLowering::Expand:
ExpandNode(Node); ExpandNode(Node);