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https://github.com/c64scene-ar/llvm-6502.git
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[mips] Modify definitions of two register operand floating point instructions.
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170069 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
82fdad75f7
commit
4b921416b4
@ -200,60 +200,92 @@ multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
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}
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}
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class ABSS_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC,
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InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
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InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
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[(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR>;
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multiclass ABSS_M<string opstr, InstrItinClass Itin,
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SDPatternOperator OpNode= null_frag> {
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def _D32 : ABSS_FT<opstr, AFGR64, AFGR64, Itin, OpNode>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def _D64 : ABSS_FT<opstr, FGR64, FGR64, Itin, OpNode>,
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Requires<[IsFP64bit, HasStdEnc]> {
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string DecoderNamespace = "Mips64";
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}
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}
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multiclass ROUND_M<string opstr, InstrItinClass Itin> {
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def _D32 : ABSS_FT<opstr, FGR32, AFGR64, Itin>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def _D64 : ABSS_FT<opstr, FGR32, FGR64, Itin>,
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Requires<[IsFP64bit, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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//===----------------------------------------------------------------------===//
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def ROUND_W_S : FFR1<0xc, 16, "round.w.s", FGR32, FGR32>;
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def TRUNC_W_S : FFR1<0xd, 16, "trunc.w.s", FGR32, FGR32>;
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def CEIL_W_S : FFR1<0xe, 16, "ceil.w.s", FGR32, FGR32>;
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def FLOOR_W_S : FFR1<0xf, 16, "floor.w.s", FGR32, FGR32>;
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def CVT_W_S : FFR1<0x24, 16, "cvt.w.s", FGR32, FGR32>, NeverHasSideEffects;
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def ROUND_W_S : ABSS_FT<"round.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xc, 16>;
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def TRUNC_W_S : ABSS_FT<"trunc.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xd, 16>;
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def CEIL_W_S : ABSS_FT<"ceil.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xe, 16>;
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def FLOOR_W_S : ABSS_FT<"floor.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0xf, 16>;
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def CVT_W_S : ABSS_FT<"cvt.w.s", FGR32, FGR32, IIFcvt>, ABSS_FM<0x24, 16>,
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NeverHasSideEffects;
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defm ROUND_W : FFR1_W_M<0xc, "round.w.d">;
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defm TRUNC_W : FFR1_W_M<0xd, "trunc.w.d">;
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defm CEIL_W : FFR1_W_M<0xe, "ceil.w.d">;
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defm FLOOR_W : FFR1_W_M<0xf, "floor.w.d">;
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defm CVT_W : FFR1_W_M<0x24, "cvt.w.d">, NeverHasSideEffects;
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defm ROUND_W : ROUND_M<"round.w.d", IIFcvt>, ABSS_FM<0xc, 17>;
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defm TRUNC_W : ROUND_M<"trunc.w.d", IIFcvt>, ABSS_FM<0xd, 17>;
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defm CEIL_W : ROUND_M<"ceil.w.d", IIFcvt>, ABSS_FM<0xe, 17>;
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defm FLOOR_W : ROUND_M<"floor.w.d", IIFcvt>, ABSS_FM<0xf, 17>;
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defm CVT_W : ROUND_M<"cvt.w.d", IIFcvt>, ABSS_FM<0x24, 17>,
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NeverHasSideEffects;
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
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def ROUND_L_S : FFR1<0x8, 16, "round.l.s", FGR64, FGR32>;
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def ROUND_L_D64 : FFR1<0x8, 17, "round.l.d", FGR64, FGR64>;
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def TRUNC_L_S : FFR1<0x9, 16, "trunc.l.s", FGR64, FGR32>;
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def TRUNC_L_D64 : FFR1<0x9, 17, "trunc.l.d", FGR64, FGR64>;
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def CEIL_L_S : FFR1<0xa, 16, "ceil.l.s", FGR64, FGR32>;
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def CEIL_L_D64 : FFR1<0xa, 17, "ceil.l.d", FGR64, FGR64>;
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def FLOOR_L_S : FFR1<0xb, 16, "floor.l.s", FGR64, FGR32>;
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def FLOOR_L_D64 : FFR1<0xb, 17, "floor.l.d", FGR64, FGR64>;
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def ROUND_L_S : ABSS_FT<"round.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x8, 16>;
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def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64, FGR64, IIFcvt>,
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ABSS_FM<0x8, 17>;
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def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x9, 16>;
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def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64, FGR64, IIFcvt>,
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ABSS_FM<0x9, 17>;
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def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xa, 16>;
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def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0xa, 17>;
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def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0xb, 16>;
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def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64, FGR64, IIFcvt>,
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ABSS_FM<0xb, 17>;
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}
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def CVT_S_W : FFR1<0x20, 20, "cvt.s.w", FGR32, FGR32>, NeverHasSideEffects;
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def CVT_L_S : FFR1<0x25, 16, "cvt.l.s", FGR64, FGR32>, NeverHasSideEffects;
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def CVT_L_D64: FFR1<0x25, 17, "cvt.l.d", FGR64, FGR64>, NeverHasSideEffects;
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def CVT_S_W : ABSS_FT<"cvt.s.w", FGR32, FGR32, IIFcvt>, ABSS_FM<0x20, 20>;
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def CVT_L_S : ABSS_FT<"cvt.l.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x25, 16>,
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NeverHasSideEffects;
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def CVT_L_D64: ABSS_FT<"cvt.l.d", FGR64, FGR64, IIFcvt>, ABSS_FM<0x25, 17>,
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NeverHasSideEffects;
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let Predicates = [NotFP64bit, HasStdEnc], neverHasSideEffects = 1 in {
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def CVT_S_D32 : FFR1<0x20, 17, "cvt.s.d", FGR32, AFGR64>;
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def CVT_D32_W : FFR1<0x21, 20, "cvt.d.w", AFGR64, FGR32>;
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def CVT_D32_S : FFR1<0x21, 16, "cvt.d.s", AFGR64, FGR32>;
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def CVT_S_D32 : ABSS_FT<"cvt.s.d", FGR32, AFGR64, IIFcvt>, ABSS_FM<0x20, 17>;
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def CVT_D32_W : ABSS_FT<"cvt.d.w", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
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def CVT_D32_S : ABSS_FT<"cvt.d.s", AFGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
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}
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let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64",
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neverHasSideEffects = 1 in {
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def CVT_S_D64 : FFR1<0x20, 17, "cvt.s.d", FGR32, FGR64>;
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def CVT_S_L : FFR1<0x20, 21, "cvt.s.l", FGR32, FGR64>;
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def CVT_D64_W : FFR1<0x21, 20, "cvt.d.w", FGR64, FGR32>;
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def CVT_D64_S : FFR1<0x21, 16, "cvt.d.s", FGR64, FGR32>;
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def CVT_D64_L : FFR1<0x21, 21, "cvt.d.l", FGR64, FGR64>;
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def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 17>;
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def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32, FGR64, IIFcvt>, ABSS_FM<0x20, 21>;
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def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 20>;
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def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64, FGR32, IIFcvt>, ABSS_FM<0x21, 16>;
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def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64, FGR64, IIFcvt>, ABSS_FM<0x21, 21>;
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}
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let Predicates = [NoNaNsFPMath, HasStdEnc] in {
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def FABS_S : FFR1P<0x5, 16, "abs.s", FGR32, FGR32, fabs>;
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def FNEG_S : FFR1P<0x7, 16, "neg.s", FGR32, FGR32, fneg>;
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defm FABS : FFR1P_M<0x5, "abs.d", fabs>;
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defm FNEG : FFR1P_M<0x7, "neg.d", fneg>;
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def FABS_S : ABSS_FT<"abs.s", FGR32, FGR32, IIFcvt, fabs>, ABSS_FM<0x5, 16>;
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def FNEG_S : ABSS_FT<"neg.s", FGR32, FGR32, IIFcvt, fneg>, ABSS_FM<0x7, 16>;
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defm FABS : ABSS_M<"abs.d", IIFcvt, fabs>, ABSS_FM<0x5, 17>;
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defm FNEG : ABSS_M<"neg.d", IIFcvt, fneg>, ABSS_FM<0x7, 17>;
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}
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def FSQRT_S : FFR1P<0x4, 16, "sqrt.s", FGR32, FGR32, fsqrt>;
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defm FSQRT : FFR1P_M<0x4, "sqrt.d", fsqrt>;
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def FSQRT_S : ABSS_FT<"sqrt.s", FGR32, FGR32, IIFsqrtSingle, fsqrt>,
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ABSS_FM<0x4, 16>;
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defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
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// The odd-numbered registers are only referenced when doing loads,
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// stores, and moves between floating-point and integer registers.
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@ -290,10 +322,10 @@ def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt),
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"dmtc1\t$rt, $fs",
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[(set FGR64:$fs, (bitconvert CPU64Regs:$rt))]>;
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def FMOV_S : FFR1<0x6, 16, "mov.s", FGR32, FGR32>;
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def FMOV_D32 : FFR1<0x6, 17, "mov.d", AFGR64, AFGR64>,
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def FMOV_S : ABSS_FT<"mov.s", FGR32, FGR32, IIFmove>, ABSS_FM<0x6, 16>;
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def FMOV_D32 : ABSS_FT<"mov.d", AFGR64, AFGR64, IIFmove>, ABSS_FM<0x6, 17>,
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Requires<[NotFP64bit, HasStdEnc]>;
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def FMOV_D64 : FFR1<0x6, 17, "mov.d", FGR64, FGR64>,
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def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>,
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Requires<[IsFP64bit, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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@ -367,3 +367,17 @@ class ADDS_FM<bits<6> funct, bits<5> fmt> {
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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class ABSS_FM<bits<6> funct, bits<5> fmt> {
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bits<5> fd;
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bits<5> fs;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = fmt;
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let Inst{20-16} = 0;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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