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clang-format ARMInstPrinter.{h,cpp} before I make changes to these files.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233448 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2015-03-27 23:24:22 +00:00
parent e464bbfb5a
commit 4bb318dc49
2 changed files with 282 additions and 267 deletions
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418
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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@@ -58,19 +58,16 @@ static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
} }
} }
ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCInstrInfo &MII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI) : const MCSubtargetInfo &STI)
MCInstPrinter(MAI, MII, MRI) { : MCInstPrinter(MAI, MII, MRI) {
// Initialize the set of available features. // Initialize the set of available features.
setAvailableFeatures(STI.getFeatureBits()); setAvailableFeatures(STI.getFeatureBits());
} }
void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
OS << markup("<reg:") OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
<< getRegisterName(RegNo)
<< markup(">");
} }
void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
@@ -84,11 +81,21 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
case ARM::tHINT: case ARM::tHINT:
case ARM::t2HINT: case ARM::t2HINT:
switch (MI->getOperand(0).getImm()) { switch (MI->getOperand(0).getImm()) {
case 0: O << "\tnop"; break; case 0:
case 1: O << "\tyield"; break; O << "\tnop";
case 2: O << "\twfe"; break; break;
case 3: O << "\twfi"; break; case 1:
case 4: O << "\tsev"; break; O << "\tyield";
break;
case 2:
O << "\twfe";
break;
case 3:
O << "\twfi";
break;
case 4:
O << "\tsev";
break;
case 5: case 5:
if ((getAvailableFeatures() & ARM::HasV8Ops)) { if ((getAvailableFeatures() & ARM::HasV8Ops)) {
O << "\tsevl"; O << "\tsevl";
@@ -150,10 +157,8 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
return; return;
} }
O << ", " O << ", " << markup("<imm:") << "#"
<< markup("<imm:") << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
<< "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
<< markup(">");
printAnnotation(O, Annot); printAnnotation(O, Annot);
return; return;
} }
@@ -255,7 +260,8 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
printPredicateOperand(MI, 1, O); printPredicateOperand(MI, 1, O);
O << '\t'; O << '\t';
printRegName(O, BaseReg); printRegName(O, BaseReg);
if (Writeback) O << "!"; if (Writeback)
O << "!";
O << ", "; O << ", ";
printRegisterList(MI, 3, O); printRegisterList(MI, 3, O);
printAnnotation(O, Annot); printAnnotation(O, Annot);
@@ -268,8 +274,10 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
// GPRs. However, when decoding them, the two GRPs cannot be automatically // GPRs. However, when decoding them, the two GRPs cannot be automatically
// expressed as a GPRPair, so we have to manually merge them. // expressed as a GPRPair, so we have to manually merge them.
// FIXME: We would really like to be able to tablegen'erate this. // FIXME: We would really like to be able to tablegen'erate this.
case ARM::LDREXD: case ARM::STREXD: case ARM::LDREXD:
case ARM::LDAEXD: case ARM::STLEXD: { case ARM::STREXD:
case ARM::LDAEXD:
case ARM::STLEXD: {
const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD; bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg(); unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
@@ -280,8 +288,8 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
if (isStore) if (isStore)
NewMI.addOperand(MI->getOperand(0)); NewMI.addOperand(MI->getOperand(0));
NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0, NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(
&MRI.getRegClass(ARM::GPRPairRegClassID))); Reg, ARM::gsub_0, &MRI.getRegClass(ARM::GPRPairRegClassID)));
NewMI.addOperand(NewReg); NewMI.addOperand(NewReg);
// Copy the rest operands into NewMI. // Copy the rest operands into NewMI.
@@ -296,8 +304,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
// For a target that has Virtualization Extensions, ERET is the preferred // For a target that has Virtualization Extensions, ERET is the preferred
// disassembly of SUBS PC, LR, #0 // disassembly of SUBS PC, LR, #0
case ARM::t2SUBS_PC_LR: { case ARM::t2SUBS_PC_LR: {
if (MI->getNumOperands() == 3 && if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() &&
MI->getOperand(0).isImm() &&
MI->getOperand(0).getImm() == 0 && MI->getOperand(0).getImm() == 0 &&
(getAvailableFeatures() & ARM::FeatureVirtualization)) { (getAvailableFeatures() & ARM::FeatureVirtualization)) {
O << "\teret"; O << "\teret";
@@ -320,9 +327,7 @@ void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
unsigned Reg = Op.getReg(); unsigned Reg = Op.getReg();
printRegName(O, Reg); printRegName(O, Reg);
} else if (Op.isImm()) { } else if (Op.isImm()) {
O << markup("<imm:") O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
<< '#' << formatImm(Op.getImm())
<< markup(">");
} else { } else {
assert(Op.isExpr() && "unknown operand kind in printOperand"); assert(Op.isExpr() && "unknown operand kind in printOperand");
const MCExpr *Expr = Op.getExpr(); const MCExpr *Expr = Op.getExpr();
@@ -370,13 +375,9 @@ void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
if (OffImm == INT32_MIN) if (OffImm == INT32_MIN)
OffImm = 0; OffImm = 0;
if (isSub) { if (isSub) {
O << markup("<imm:") O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
<< "#-" << formatImm(-OffImm)
<< markup(">");
} else { } else {
O << markup("<imm:") O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
<< "#" << formatImm(OffImm)
<< markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
} }
@@ -417,7 +418,6 @@ void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup); ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
} }
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
// Addressing Mode #2 // Addressing Mode #2
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
@@ -433,12 +433,9 @@ void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
if (!MO2.getReg()) { if (!MO2.getReg()) {
if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0. if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
O << ", " O << ", " << markup("<imm:") << "#"
<< markup("<imm:")
<< "#"
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm())) << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
<< ARM_AM::getAM2Offset(MO3.getImm()) << ARM_AM::getAM2Offset(MO3.getImm()) << markup(">");
<< markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
return; return;
@@ -487,8 +484,7 @@ void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
#ifndef NDEBUG #ifndef NDEBUG
const MCOperand &MO3 = MI->getOperand(Op + 2); const MCOperand &MO3 = MI->getOperand(Op + 2);
unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm()); unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
assert(IdxMode != ARMII::IndexModePost && assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
"Should be pre or offset index op");
#endif #endif
printAM2PreOrOffsetIndexOp(MI, Op, O); printAM2PreOrOffsetIndexOp(MI, Op, O);
@@ -502,9 +498,8 @@ void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
if (!MO1.getReg()) { if (!MO1.getReg()) {
unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm()); unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
O << markup("<imm:") O << markup("<imm:") << '#'
<< '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm())) << ImmOffs
<< ImmOffs
<< markup(">"); << markup(">");
return; return;
} }
@@ -542,11 +537,7 @@ void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm()); ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) { if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
O << ", " O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(op) << ImmOffs
<< markup("<imm:")
<< "#"
<< ARM_AM::getAddrOpcStr(op)
<< ImmOffs
<< markup(">"); << markup(">");
} }
O << ']' << markup(">"); O << ']' << markup(">");
@@ -580,18 +571,16 @@ void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
} }
unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm()); unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
O << markup("<imm:") O << markup("<imm:") << '#'
<< '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
<< markup(">"); << markup(">");
} }
void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum,
unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum); const MCOperand &MO = MI->getOperand(OpNum);
unsigned Imm = MO.getImm(); unsigned Imm = MO.getImm();
O << markup("<imm:") O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
<< '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
<< markup(">"); << markup(">");
} }
@@ -604,21 +593,18 @@ void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
printRegName(O, MO1.getReg()); printRegName(O, MO1.getReg());
} }
void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum,
unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum); const MCOperand &MO = MI->getOperand(OpNum);
unsigned Imm = MO.getImm(); unsigned Imm = MO.getImm();
O << markup("<imm:") O << markup("<imm:") << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
<< '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
<< markup(">"); << markup(">");
} }
void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum) ARM_AM::AMSubMode Mode =
.getImm()); ARM_AM::getAM4SubMode(MI->getOperand(OpNum).getImm());
O << ARM_AM::getAMSubModeStr(Mode); O << ARM_AM::getAMSubModeStr(Mode);
} }
@@ -639,12 +625,8 @@ void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm()); unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm()); ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) { if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
O << ", " O << ", " << markup("<imm:") << "#" << ARM_AM::getAddrOpcStr(Op)
<< markup("<imm:") << ImmOffs * 4 << markup(">");
<< "#"
<< ARM_AM::getAddrOpcStr(Op)
<< ImmOffs * 4
<< markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
} }
@@ -690,9 +672,8 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
int32_t lsb = countTrailingZeros(v); int32_t lsb = countTrailingZeros(v);
int32_t width = (32 - countLeadingZeros(v)) - lsb; int32_t width = (32 - countLeadingZeros(v)) - lsb;
assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!"); assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
O << markup("<imm:") << '#' << lsb << markup(">") O << markup("<imm:") << '#' << lsb << markup(">") << ", " << markup("<imm:")
<< ", " << '#' << width << markup(">");
<< markup("<imm:") << '#' << width << markup(">");
} }
void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
@@ -713,16 +694,10 @@ void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
bool isASR = (ShiftOp & (1 << 5)) != 0; bool isASR = (ShiftOp & (1 << 5)) != 0;
unsigned Amt = ShiftOp & 0x1f; unsigned Amt = ShiftOp & 0x1f;
if (isASR) { if (isASR) {
O << ", asr " O << ", asr " << markup("<imm:") << "#" << (Amt == 0 ? 32 : Amt)
<< markup("<imm:")
<< "#" << (Amt == 0 ? 32 : Amt)
<< markup(">");
}
else if (Amt) {
O << ", lsl "
<< markup("<imm:")
<< "#" << Amt
<< markup(">"); << markup(">");
} else if (Amt) {
O << ", lsl " << markup("<imm:") << "#" << Amt << markup(">");
} }
} }
@@ -749,7 +724,8 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
O << "{"; O << "{";
for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
if (i != OpNum) O << ", "; if (i != OpNum)
O << ", ";
printRegName(O, MI->getOperand(i).getReg()); printRegName(O, MI->getOperand(i).getReg());
} }
O << "}"; O << "}";
@@ -763,7 +739,6 @@ void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1)); printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
} }
void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNum); const MCOperand &Op = MI->getOperand(OpNum);
@@ -805,14 +780,30 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
// For writes, handle extended mask bits if the DSP extension is present. // For writes, handle extended mask bits if the DSP extension is present.
if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) { if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) {
switch (SYSm) { switch (SYSm) {
case 0x400: O << "apsr_g"; return; case 0x400:
case 0xc00: O << "apsr_nzcvqg"; return; O << "apsr_g";
case 0x401: O << "iapsr_g"; return; return;
case 0xc01: O << "iapsr_nzcvqg"; return; case 0xc00:
case 0x402: O << "eapsr_g"; return; O << "apsr_nzcvqg";
case 0xc02: O << "eapsr_nzcvqg"; return; return;
case 0x403: O << "xpsr_g"; return; case 0x401:
case 0xc03: O << "xpsr_nzcvqg"; return; O << "iapsr_g";
return;
case 0xc01:
O << "iapsr_nzcvqg";
return;
case 0x402:
O << "eapsr_g";
return;
case 0xc02:
O << "eapsr_nzcvqg";
return;
case 0x403:
O << "xpsr_g";
return;
case 0xc03:
O << "xpsr_nzcvqg";
return;
} }
} }
@@ -823,29 +814,66 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
// ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
// alias for MSR APSR_nzcvq. // alias for MSR APSR_nzcvq.
switch (SYSm) { switch (SYSm) {
case 0: O << "apsr_nzcvq"; return; case 0:
case 1: O << "iapsr_nzcvq"; return; O << "apsr_nzcvq";
case 2: O << "eapsr_nzcvq"; return; return;
case 3: O << "xpsr_nzcvq"; return; case 1:
O << "iapsr_nzcvq";
return;
case 2:
O << "eapsr_nzcvq";
return;
case 3:
O << "xpsr_nzcvq";
return;
} }
} }
switch (SYSm) { switch (SYSm) {
default: llvm_unreachable("Unexpected mask value!"); default:
case 0: O << "apsr"; return; llvm_unreachable("Unexpected mask value!");
case 1: O << "iapsr"; return; case 0:
case 2: O << "eapsr"; return; O << "apsr";
case 3: O << "xpsr"; return; return;
case 5: O << "ipsr"; return; case 1:
case 6: O << "epsr"; return; O << "iapsr";
case 7: O << "iepsr"; return; return;
case 8: O << "msp"; return; case 2:
case 9: O << "psp"; return; O << "eapsr";
case 16: O << "primask"; return; return;
case 17: O << "basepri"; return; case 3:
case 18: O << "basepri_max"; return; O << "xpsr";
case 19: O << "faultmask"; return; return;
case 20: O << "control"; return; case 5:
O << "ipsr";
return;
case 6:
O << "epsr";
return;
case 7:
O << "iepsr";
return;
case 8:
O << "msp";
return;
case 9:
O << "psp";
return;
case 16:
O << "primask";
return;
case 17:
O << "basepri";
return;
case 18:
O << "basepri_max";
return;
case 19:
O << "faultmask";
return;
case 20:
O << "control";
return;
} }
} }
@@ -854,10 +882,17 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
O << "APSR_"; O << "APSR_";
switch (Mask) { switch (Mask) {
default: llvm_unreachable("Unexpected mask value!"); default:
case 4: O << "g"; return; llvm_unreachable("Unexpected mask value!");
case 8: O << "nzcvq"; return; case 4:
case 12: O << "nzcvqg"; return; O << "g";
return;
case 8:
O << "nzcvq";
return;
case 12:
O << "nzcvqg";
return;
} }
} }
@@ -868,10 +903,14 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
if (Mask) { if (Mask) {
O << '_'; O << '_';
if (Mask & 8) O << 'f'; if (Mask & 8)
if (Mask & 4) O << 's'; O << 'f';
if (Mask & 2) O << 'x'; if (Mask & 4)
if (Mask & 1) O << 'c'; O << 's';
if (Mask & 2)
O << 'x';
if (Mask & 1)
O << 'c';
} }
} }
@@ -887,24 +926,39 @@ void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
O << "SPSR_"; O << "SPSR_";
switch (SysM) { switch (SysM) {
case 0x0e: O << "fiq"; return; case 0x0e:
case 0x10: O << "irq"; return; O << "fiq";
case 0x12: O << "svc"; return; return;
case 0x14: O << "abt"; return; case 0x10:
case 0x16: O << "und"; return; O << "irq";
case 0x1c: O << "mon"; return; return;
case 0x1e: O << "hyp"; return; case 0x12:
default: llvm_unreachable("Invalid banked SPSR register"); O << "svc";
return;
case 0x14:
O << "abt";
return;
case 0x16:
O << "und";
return;
case 0x1c:
O << "mon";
return;
case 0x1e:
O << "hyp";
return;
default:
llvm_unreachable("Invalid banked SPSR register");
} }
} }
assert(!R && "should have dealt with SPSR regs"); assert(!R && "should have dealt with SPSR regs");
const char *RegNames[] = { const char *RegNames[] = {
"r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", "", "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr",
"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq", "", "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq",
"lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", "sp_abt", "lr_und", "sp_und", "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt",
"", "", "", "", "lr_mon", "sp_mon", "elr_hyp", "sp_hyp" "sp_abt", "lr_und", "sp_und", "", "", "", "",
}; "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"};
const char *Name = RegNames[SysM]; const char *Name = RegNames[SysM];
assert(Name[0] && "invalid banked register operand"); assert(Name[0] && "invalid banked register operand");
@@ -986,16 +1040,14 @@ void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
O << markup("<imm:") O << markup("<imm:") << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
<< "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
<< markup(">"); << markup(">");
} }
void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNum).getImm(); unsigned Imm = MI->getOperand(OpNum).getImm();
O << markup("<imm:") O << markup("<imm:") << "#" << formatImm((Imm == 0 ? 32 : Imm))
<< "#" << formatImm((Imm == 0 ? 32 : Imm))
<< markup(">"); << markup(">");
} }
@@ -1036,8 +1088,7 @@ void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
} }
void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI, void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
unsigned Op, unsigned Op, raw_ostream &O,
raw_ostream &O,
unsigned Scale) { unsigned Scale) {
const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO1 = MI->getOperand(Op);
const MCOperand &MO2 = MI->getOperand(Op + 1); const MCOperand &MO2 = MI->getOperand(Op + 1);
@@ -1050,9 +1101,7 @@ void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
O << markup("<mem:") << "["; O << markup("<mem:") << "[";
printRegName(O, MO1.getReg()); printRegName(O, MO1.getReg());
if (unsigned ImmOffs = MO2.getImm()) { if (unsigned ImmOffs = MO2.getImm()) {
O << ", " O << ", " << markup("<imm:") << "#" << formatImm(ImmOffs * Scale)
<< markup("<imm:")
<< "#" << formatImm(ImmOffs * Scale)
<< markup(">"); << markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
@@ -1119,16 +1168,9 @@ void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
if (OffImm == INT32_MIN) if (OffImm == INT32_MIN)
OffImm = 0; OffImm = 0;
if (isSub) { if (isSub) {
O << ", " O << ", " << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
<< markup("<imm:") } else if (AlwaysPrintImm0 || OffImm > 0) {
<< "#-" << formatImm(-OffImm) O << ", " << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
<< markup(">");
}
else if (AlwaysPrintImm0 || OffImm > 0) {
O << ", "
<< markup("<imm:")
<< "#" << formatImm(OffImm)
<< markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
} }
@@ -1149,15 +1191,9 @@ void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
if (OffImm == INT32_MIN) if (OffImm == INT32_MIN)
OffImm = 0; OffImm = 0;
if (isSub) { if (isSub) {
O << ", " O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
<< markup("<imm:")
<< "#-" << -OffImm
<< markup(">");
} else if (AlwaysPrintImm0 || OffImm > 0) { } else if (AlwaysPrintImm0 || OffImm > 0) {
O << ", " O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
<< markup("<imm:")
<< "#" << OffImm
<< markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
} }
@@ -1186,15 +1222,9 @@ void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
if (OffImm == INT32_MIN) if (OffImm == INT32_MIN)
OffImm = 0; OffImm = 0;
if (isSub) { if (isSub) {
O << ", " O << ", " << markup("<imm:") << "#-" << -OffImm << markup(">");
<< markup("<imm:")
<< "#-" << -OffImm
<< markup(">");
} else if (AlwaysPrintImm0 || OffImm > 0) { } else if (AlwaysPrintImm0 || OffImm > 0) {
O << ", " O << ", " << markup("<imm:") << "#" << OffImm << markup(">");
<< markup("<imm:")
<< "#" << OffImm
<< markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
} }
@@ -1208,9 +1238,7 @@ void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
O << markup("<mem:") << "["; O << markup("<mem:") << "[";
printRegName(O, MO1.getReg()); printRegName(O, MO1.getReg());
if (MO2.getImm()) { if (MO2.getImm()) {
O << ", " O << ", " << markup("<imm:") << "#" << formatImm(MO2.getImm() * 4)
<< markup("<imm:")
<< "#" << formatImm(MO2.getImm() * 4)
<< markup(">"); << markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
@@ -1266,10 +1294,7 @@ void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
unsigned ShAmt = MO3.getImm(); unsigned ShAmt = MO3.getImm();
if (ShAmt) { if (ShAmt) {
assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!"); assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
O << ", lsl " O << ", lsl " << markup("<imm:") << "#" << ShAmt << markup(">");
<< markup("<imm:")
<< "#" << ShAmt
<< markup(">");
} }
O << "]" << markup(">"); O << "]" << markup(">");
} }
@@ -1277,8 +1302,7 @@ void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum); const MCOperand &MO = MI->getOperand(OpNum);
O << markup("<imm:") O << markup("<imm:") << '#' << ARM_AM::getFPImmFloat(MO.getImm())
<< '#' << ARM_AM::getFPImmFloat(MO.getImm())
<< markup(">"); << markup(">");
} }
@@ -1287,8 +1311,7 @@ void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
unsigned EncodedImm = MI->getOperand(OpNum).getImm(); unsigned EncodedImm = MI->getOperand(OpNum).getImm();
unsigned EltBits; unsigned EltBits;
uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
O << markup("<imm:") O << markup("<imm:") << "#0x";
<< "#0x";
O.write_hex(Val); O.write_hex(Val);
O << markup(">"); O << markup(">");
} }
@@ -1296,9 +1319,7 @@ void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNum).getImm(); unsigned Imm = MI->getOperand(OpNum).getImm();
O << markup("<imm:") O << markup("<imm:") << "#" << formatImm(Imm + 1) << markup(">");
<< "#" << formatImm(Imm + 1)
<< markup(">");
} }
void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
@@ -1306,14 +1327,19 @@ void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
unsigned Imm = MI->getOperand(OpNum).getImm(); unsigned Imm = MI->getOperand(OpNum).getImm();
if (Imm == 0) if (Imm == 0)
return; return;
O << ", ror " O << ", ror " << markup("<imm:") << "#";
<< markup("<imm:")
<< "#";
switch (Imm) { switch (Imm) {
default: assert (0 && "illegal ror immediate!"); default:
case 1: O << "8"; break; assert(0 && "illegal ror immediate!");
case 2: O << "16"; break; case 1:
case 3: O << "24"; break; O << "8";
break;
case 2:
O << "16";
break;
case 3:
O << "24";
break;
} }
O << markup(">"); O << markup(">");
} }
@@ -1354,27 +1380,19 @@ void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
} }
// Explicit #bits, #rot implied // Explicit #bits, #rot implied
O << "#" O << "#" << markup("<imm:") << Bits << markup(">") << ", #" << markup("<imm:")
<< markup("<imm:") << Rot << markup(">");
<< Bits
<< markup(">")
<< ", #"
<< markup("<imm:")
<< Rot
<< markup(">");
} }
void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
O << markup("<imm:") O << markup("<imm:") << "#" << 16 - MI->getOperand(OpNum).getImm()
<< "#" << 16 - MI->getOperand(OpNum).getImm()
<< markup(">"); << markup(">");
} }
void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum, void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
O << markup("<imm:") O << markup("<imm:") << "#" << 32 - MI->getOperand(OpNum).getImm()
<< "#" << 32 - MI->getOperand(OpNum).getImm()
<< markup(">"); << markup(">");
} }
@@ -1402,8 +1420,7 @@ void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
O << "}"; O << "}";
} }
void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg = MI->getOperand(OpNum).getReg();
unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
@@ -1558,8 +1575,7 @@ void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
O << "}"; O << "}";
} }
void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
unsigned OpNum,
raw_ostream &O) { raw_ostream &O) {
// Normally, it's not safe to use register enum values directly with // Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the // addition to get the next register, but for VFP registers, the

1
lib/Target/ARM/InstPrinter/ARMInstPrinter.h
View File

@@ -34,7 +34,6 @@ public:
void printInstruction(const MCInst *MI, raw_ostream &O); void printInstruction(const MCInst *MI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo); static const char *getRegisterName(unsigned RegNo);
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);